W83627EG Nuvoton Technology Corporation of America, W83627EG Datasheet - Page 238

• Manufacturer Part Number: W83627EG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CR E5h. (Reserved)
CR E6h. (Default 1Ch)
BIT
7~0
1~0
BIT
BIT
7
6
5
4
3
2
Reserved.
READ / WRITE
Reserved.
READ / WRITE
Reserved.
READ / WRITE
R / W
R / W
R / W
R / W
R / W
ENMDAT =>
3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1])
define the combinations of the mouse wake-up events. Please check out the
table in CRE0[4] for the detailed.
CASEOPEN Clear Control.
Write 1 to this bit will clear CASEOPEN status.
please write 0 after event be cleared. The function is as same as Index 46h bit
7 of H/W Monitor part.
Power loss Last State Flag. (VBAT)
0: ON
1: OFF.
PWROK_DEL (first stage)
Set the delay rising time from PWROK_LP to PWROK_ST.
0: 300 ~ 600 ms.
1: 200 ~ 300 ms.
Enable the hunting mode for all wake-up events set in CRE0. This bit is
cleared when any wake-up events is captured.
0: Disable.
1: Enable.
(VSB)
W83627EHF/EF, W83627EHG/EG
-227-
(VSB)
(VSB)
DESCRIPTION
DESCRIPTION
DESCRIPTION
Publication Release Date: April 7, 2009
(LRESET#)
This bit won’t be self cleared,
Version 1.94