M25PX64-VMF6TP Micron Technology Inc, M25PX64-VMF6TP Datasheet - Page 32

• Manufacturer Part Number: M25PX64-VMF6TP
• Manufacturer: Micron Technology Inc

Specifications of M25PX64-VMF6TP

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Address Bus: 24b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 8M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.4
6.4.1
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6.4.3
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Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status
register may be read at any time, even while a program, erase or write status register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
write in progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the status register continuously, as shown in
Table 7.
The status and control bits of the status register are as follows:
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write status
register, program or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to
‘0’ no such cycle is in progress.
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When
set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is
reset and no write status register, program or erase instruction is accepted.
BP2, BP1, BP0 bits
The block protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against program and erase instructions. These bits are written with
the write status register (WRSR) instruction. When one or more of the block protect (BP2,
BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in
protected against page program (PP) and sector erase (SE) instructions. The block protect
(BP2, BP1, BP0) bits can be written provided that the hardware protected mode has not
been set. The bulk erase (BE) instruction is executed if, and only if, all block protect (BP2,
BP1, BP0) bits are 0.
Status register write protect
SRWD
b7
Status register format
0
Top/bottom bit
TB
BP2
Block protect bits
Figure
BP1
12.
Write enable latch bit
BP0
Table
WEL
Write in progress bit
3) becomes
WIP
b0