M25PX64-VMF6TP Micron Technology Inc, M25PX64-VMF6TP Datasheet - Page 39
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M25PX64-VMF6TP
Manufacturer Part Number
M25PX64-VMF6TP
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M25PX64-VMF6TP.pdf
(70 pages)
Specifications of M25PX64-VMF6TP
Cell Type
NOR
Density
64Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Address Bus
24b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
8M
Supply Current
12mA
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25PX64-VMF6TP
Manufacturer:
NUMONYX
Quantity:
5 100
Part Number:
M25PX64-VMF6TP
Manufacturer:
ST
Quantity:
20 000
6.9
Read lock register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
lock register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the lock register is shifted out on serial data output
(DQ1), each bit being shifted out, at a maximum frequency f
Serial Clock (C).
The instruction sequence is shown in
The read lock register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any read lock register (RDLR) instruction, while an erase, program or write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Table 9.
1. Values of (b1, b0) after power-up are defined in
Figure 17. Read lock register (RDLR) instruction sequence and data-out sequence
DQ0
DQ1
b7-b2
Bit
b1
b0
C
S
Sector lock down
Sector write lock
Lock register out
Bit name
0
1
High Impedance
2
Instruction
3
4
5
Value
‘1’
‘0’
‘1’
‘0’
6
(1)
7
MSB
23
The write lock and lock down bits cannot be changed. Once a
‘1’ is written to the lock down bit it cannot be cleared to ‘0’,
except by a power-up.
The write lock and lock down bits can be changed by writing
new values to them.
Write, program and erase operations in this sector will not be
executed. The memory contents will not be changed.
Write, program and erase operations in this sector are
executed and will modify the sector contents.
8
Figure
22 21
9 10
24-bit address
Section 7: Power-up and
17.
Reserved
3
28 29 30 31 32 33 34 35
2
1
0
MSB
Function
7
C
, during the falling edge of
6
power-down.
Lock register out
5
4
3
36 37 38
2
1
0
39
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