M25PX64-VMF6TP Micron Technology Inc, M25PX64-VMF6TP Datasheet - Page 45

• Manufacturer Part Number: M25PX64-VMF6TP
• Manufacturer: Micron Technology Inc

Specifications of M25PX64-VMF6TP

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Address Bus: 24b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 8M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.13
Program OTP instruction (POTP)
The program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from ‘1’ to ‘0’, only). Before it can be accepted, a write
enable (WREN) instruction must previously have been executed. After the write enable
(WREN) instruction has been decoded, the device sets the write enable latch (WEL) bit.
The program OTP instruction is entered by driving Chip Select (S) Low, followed by the
instruction opcode, three address bytes and at least one data byte on serial data input
(DQ0).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the program OTP instruction is not executed.
There is no rollover mechanism with the program OTP (POTP) instruction. This means that
the program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,
once all 65 bytes have been latched in, any following byte will be discarded.
The instruction sequence is shown in
As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose
duration is t
may be read to check the value of the write in progress (WIP) bit. The write in progress
(WIP) bit is 1 during the self-timed program OTP cycle, and it is 0 when it is completed. At
some unspecified time before the cycle is complete, the write enable latch (WEL) bit is
reset.
To lock the OTP memory:
Bit 0 of the OTP control byte, that is byte 64, (see
OTP memory array.
Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’.
Therefore, as soon as bit 0 of byte 64 (control byte) is set to ‘0’, the 64 bytes of the OTP
memory array become read-only in a permanent way.
Any program OTP (POTP) instruction issued while an erase, program or write cycle is in
progress is rejected without having any effect on the cycle that is in progress.
When bit 0 of byte 64 = ’1’, the 64 bytes of the OTP memory array can be programmed.
When bit 0 of byte 64 = ‘0’, the 64 bytes of the OTP memory array are read-only and
cannot be programmed anymore.
PP
) is initiated. While the program OTP cycle is in progress, the status register
Figure
21.
Figure
22) is used to permanently lock the
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