MAX5971BETI+ Maxim Integrated Products, MAX5971BETI+ Datasheet - Page 16

• Manufacturer Part Number: MAX5971BETI+
• Description: Hot Swap & Power Distribution IEEE 802.3af/at PSE Controller
• Manufacturer: Maxim Integrated Products

Specifications of MAX5971BETI+

• Lead Free Status / Rohs Status: Details

Single-Port, 40W, IEEE 802.3af/at,
PSE Controller with I
Table 1. PSE PI Detection Modes Electrical Requirements (IEEE 802.3at)
execution, the command is cleared from the register(s).
PWR_ON has highest priority. Setting PWR_ON to 1 at
any time causes the device to immediately enter the
powered mode. Setting DET_EN and CLASS_EN to 1 at
the same time causes detection to be performed first.
Once in the powered state, the device ignores DET_EN
or CLASS_EN commands.
When switching to manual mode from another mode,
DET_EN and CLASS_EN default to low. These bits
become pushbutton rather than configuration bits. Writing
1 to these bits while in manual mode commands the
device to execute one cycle of detection and/or classifica-
tion. They are reset back to 0 at the end of the execution.
To put the MAX5971B into shutdown mode, set P_M[1:0]
(R12h[1:0]) to [00] during normal operation (see Table 18
and Table 19). Putting the MAX5971B into shutdown mode
immediately turns off port power, clears the event and sta-
tus bits, and halts all port operations. In shutdown mode
the serial interface is still fully active, however, all DET_EN,
CLASS_EN, and PWR_ON commands are ignored.
During normal operation, the MAX5971B probes the
output for a valid PD. A valid PD has a 25kI discov-
ery signature characteristic as specified in the IEEE
802.3af/802.3at standard. Table 1 shows the IEEE 802.3at
specification for a PSE detecting a valid PD signature.
After each detection cycle, the MAX5971B sets DET_
END (R04h[0] and R05h[0]) to 1 and reports the detec-
tion results in the detection status bits, DET_ST[2:0]
16
Open-Circuit Voltage
Short-Circuit Current
Valid Test Voltage
Voltage Difference Between Test Points
Time Between Any Two Test Points
Slew Rate
Accept Signature Resistance
Reject Signature Resistance
Open-Circuit Resistance
Accept Signature Capacitance
Reject Signature Capacitance
Signature Offset Voltage Tolerance
Signature Offset Current Tolerance
_____________________________________________________________________________________
PARAMETER
SYMBOL
R
C
DV
V
R
V
C
R
GOOD
GOOD
V
VALID
V
SLEW
OPEN
Shutdown Mode
I
t
I
PD Detection
BAD
BAD
SC
TEST
BP
OS
OC
OS
< 15
MIN
500
2.8
19
10
1
2
0
0
2
MAX
C
> 33
26.5
150
0.1
2.0
30
10
12
5
UNITS
(R0Ch[2:0], see Table 13). The DET_END registers are
reset to 0 when read through the CoR (clear-on-read)
register R05h[0], or after a reset event.
During detection, the MAX5971B keeps the internal
MOSFET off and forces two probe voltages through DET.
The current through DET is measured as well as the volt-
age at OUT. A two-point slope measurement is used,
as specified by the IEEE 802.3af/802.3at standard, to
verify the device connected to the port. By default, The
MAX5971B load stability check is disabled. Set LSC_EN
(R29h[4], Table 35) to 1 to enable the load stability
check. The MAX5971B implements appropriate settling
times to reject 50Hz/60Hz power-line noise coupling.
An external diode, in series with the DET input, restricts
PD detection to the first quadrant as specified by the
IEEE 802.3af/802.3at standard. To prevent damage to
non-PD devices, and to protect itself from an output short
circuit, the MAX5971B limits the current into DET to less
than 2mA (max) during PD detection.
In midspan mode, after every failed detection cycle, the
MAX5971B waits at least 2.0s before attempting another
detection cycle. The first detection, however, still hap-
pens immediately after exiting a reset condition.
High-capacitance detection for legacy PDs is both soft-
ware and pin programmable (LEGACY). To use software
to enable high-capacitance detection, set CLC_EN
(R23h[5]) to 1 during normal operation. Alternatively,
the status of the LEGACY input is latched and writ-
ten to CLC_EN during power-up or after reset condi-
tion is cleared. The LEGACY input is internally pulled
V/Fs
mA
ms
kI
kI
kI
nF
FF
FA
V
V
V
V
In detection mode only
In detection mode only
This timing implies a 500Hz maximum probing frequency
ADDITIONAL INFORMATION
High-Capacitance Detection