MAX5971BETI+ Maxim Integrated Products, MAX5971BETI+ Datasheet - Page 23

• Manufacturer Part Number: MAX5971BETI+
• Description: Hot Swap & Power Distribution IEEE 802.3af/at PSE Controller
• Manufacturer: Maxim Integrated Products

Specifications of MAX5971BETI+

• Lead Free Status / Rohs Status: Details

Figure 7. START and STOP Conditions
Figure 8. Bit Transfer
Figure 9. Acknowledge
Each transmission consists of a START condition sent by
a master, followed by the MAX5971B 7-bit slave address
plus R/W bit, a register address byte, one or more data
bytes, and finally a STOP condition.
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high. When the master finishes
communicating with the slave, the master issues a STOP
condition by transitioning SDA from low to high while
SCL is high. The stop condition frees the bus for another
transmission (see Figure 7).
______________________________________________________________________________________
START and STOP Conditions
TRANSMITTER
RECEIVER
SDA
SCL
SDA BY
SDA BY
SDA
SCL
SCL
Single-Port, 40W, IEEE 802.3af/at,
START
CONDITION
Serial-Addressing
S
START
DATA LINE STABLE;
S
DATA VALID
1
DATA ALLOWED
CHANGE OF
2
PSE Controller with I
Each clock pulse transfers one data bit (Figure 8). The
data on SDA must remain stable while SCL is high.
The acknowledge bit is a clocked 9th bit (Figure 9), which
the recipient uses to handshake receipt of each byte of
data. Thus each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse, so that the SDA line is stable low during the high
period of the clock pulse. When the master transmits to
the MAX5971B, the device generates the acknowledge
bit. When the MAX5971B transmits to the master, the
master generates the acknowledge bit.
ACKNOWLEDGEMENT
CLOCK PULSE FOR
8
STOP
P
9
Acknowledge
Bit Transfer
2
C
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