MAX5971BETI+ Maxim Integrated Products, MAX5971BETI+ Datasheet - Page 43

• Manufacturer Part Number: MAX5971BETI+
• Description: Hot Swap & Power Distribution IEEE 802.3af/at PSE Controller
• Manufacturer: Maxim Integrated Products

Specifications of MAX5971BETI+

• Lead Free Status / Rohs Status: Details

Table 40. Register Summary (continued)
Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimal
performance.
1) Place the high-frequency input bypass capacitor (0.1FF
2) Use large SMT component pads for power dissipat-
Figure 15. Typical Operating Circuit 1 (DC Load Removal Detection, Internal PWM Enabled for LED Indication, and Class 5
Detection Enabled)
CURRENT READOUT
ADDR REGISTER NAME
30H
31H
32H
33H
34H
35H
36H
37H
ceramic capacitor from AGND to V
bypass capacitor (0.1FF ceramic capacitor from AGND
to OUTP) as close as possible to the MAX5971B.
ing devices, such as the MAX5971B and the external
diodes in the high-power path.
Port Current (MSB)
Port Current (LSB)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Applications Information
______________________________________________________________________________________
-54V
100V
47µF
R/W
—
—
—
—
—
—
R
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.1µF
IPD[8]
100V
BIT 7
Layout Procedure
Single-Port, 40W, IEEE 802.3af/at,
EE
1N4448
) and the output
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPD[7]
BIT 6
5.1kI
LED
1nF
10mH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPD[6]
BIT 5
LED
EN
V
V
LEGACY
MIDSPAN
OSC
EE
EE_DIG
SDA
SERIAL INTERFACE
PSE Controller with I
SCL
MAX5971B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AGND
3) Use short, wide traces whenever possible for high-
4) Use the MAX5971B Evaluation Kit as a design and
5) The EP must be soldered evenly to the PCB ground
IPD[5]
BIT 4
SMJ58A
power paths.
layout reference.
plane (V
tion. Use multiple vias beneath the EP for maximum
heat dissipation. A 1.0mm to 1.2mm pitch is the
recommended spacing for these vias and should
be plated (1oz copper) with a small barrel diameter
(0.30mm to 0.33mm).
AD0
PWMEN
OUTP
ILIM1
ILIM2
INT
OUT
DET
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPD[4]
BIT 3
0.1µF
EE
100V
) for proper operation and power dissipa-
1kI
1kI
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPD[3]
BIT 2
1N4448
2.2MI
PSE OUTPUT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-54V
IPD[2]
BIT 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPD[1]
IPD[0]
BIT 0
RESET
STATE
0000 to
0000 to
0000
0000
2
—
—
—
—
—
—
C
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