MAX5971BETI+ Maxim Integrated Products, MAX5971BETI+ Datasheet - Page 27

• Manufacturer Part Number: MAX5971BETI+
• Description: Hot Swap & Power Distribution IEEE 802.3af/at PSE Controller
• Manufacturer: Maxim Integrated Products

Specifications of MAX5971BETI+

• Lead Free Status / Rohs Status: Details

The interrupt mask register (R01h, Table 8) contains
MASK_ bits that mask the corresponding interrupt bits
in register R00h (active high). Setting MASK_ bits low
individually disables the corresponding interrupt signal.
When masked (set low), the corresponding bits are still
set in the interrupt register (R00h) but the masking bit
(R01h) suppresses the generation of an interrupt signal
(INT). On power-up or a reset condition, the interrupt
mask register is set to a default state of A4h.
Table 8. Interrupt Mask Register
Table 9. Power Event Register
PWEN_CHG
SYMBOL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYMBOL
Reserved
PG_CHG
MASK7
MASK5
MASK4
MASK3
MASK2
MASK1
MASK0
ADDRESS =
ADDRESS = 01h
BIT NO.
BIT NO.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
______________________________________________________________________________________
Interrupt Mask Register (R01h)
TYPE
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
02h
—
—
—
—
—
—
R
R
Interrupt mask bit 7. A logic-high enables the SUP_INT interrupts. A logic-low disables the
SUP_FLT interrupts.
Reserved
Interrupt mask bit 5. A logic-high enables the IMAX_INT interrupts. A logic-low disables the
IMAX_FLT interrupts.
Interrupt mask bit 4. A logic-high enables the CL_INT interrupts. A logic-low disables the
CL_END interrupts.
Interrupt mask bit 3. A logic-high enables the DET_INT interrupts. A logic-low disables the
DET_END interrupts.
Interrupt mask bit 2. A logic-high enables the LD_INT interrupts. A logic-low disables the
LD_DISC interrupts.
Interrupt mask bit 1. A logic-high enables the PG_INT interrupts. A logic-low disables the
PG_INT interrupts.
Interrupt mask bit 0. A logic-high enables the PE_INT interrupts. A logic-low disables the
PE_INT interrupts.
Single-Port, 40W, IEEE 802.3af/at,
R/W
CoR
CoR
03h
—
—
—
—
—
—
Reserved
Reserved
Reserved
PGOOD change event for the port
Reserved
Reserved
Reserved
Power enable change event for the port
PSE Controller with I
The power event register (R02h/R03h, Table 9) records
changes in the power status of the port. On power-up or
after a reset condition, the power event register is set to
a default value of 00h. Any change in PGOOD (R10h[4])
sets PG_CHG to 1. Any change in PWR_EN (R10h[0])
sets PWEN_CHG to 1. PG_CHG and PWEN_CHG trig-
ger on the edges of PGOOD and PWR_EN and do not
depend on the actual logic status of the bits. The power
event register has two addresses. When read through
the R02h address, the content of the register is left
unchanged. When read through the CoR R03h address,
the register content is reset to the default state.
DESCRIPTION
The Event Registers (R02h to R08h)
DESCRIPTION
Power Event Register (R02h/R03h)
2
C
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