L80227-LEADFREE LSI, L80227-LEADFREE Datasheet - Page 26

• Manufacturer Part Number: L80227-LEADFREE
• Manufacturer: LSI

Specifications of L80227-LEADFREE

• Lead Free Status / Rohs Status: Compliant

2.3 Block Diagram Description
2.3.1 Oscillator and Clock
2-8
The L80227 PHY device has the following main blocks:
A Management Interface (MI) serial port provides access to eight internal
PHY registers.
Figure 2.1
The following sections describe each of the blocks in
performance of the device in both the 10 and 100 Mbits/s modes is
described.
The L80227 requires a 25 MHz reference frequency for internal signal
generation. This 25 MHz reference frequency is generated with either an
external 25 MHz crystal connected between OSCIN and GND or with the
application of an external 25 MHz clock to OSCIN.
The device provides either a 2.5 MHz or 25 MHz reference clock at the
TX_CLK or RX_CLK output pins for 10-MHz or 100 MHz operation,
respectively.
Functional Description
Oscillator and Clock
Controller Interface
4B5B/Manchester Encoder/Decoder
Scrambler/Descrambler
Twisted-Pair Transmitter
Twisted-Pair Receiver
Clock and Data Recovery
Link Integrity/AutoNegotiation
Descrambler
Link Indication
Collision Detection
LED Drivers
shows the main blocks, along with their associated signals.
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Figure
2.1. The