L80227-LEADFREE LSI, L80227-LEADFREE Datasheet - Page 36

• Manufacturer Part Number: L80227-LEADFREE
• Manufacturer: LSI

Specifications of L80227-LEADFREE

• Lead Free Status / Rohs Status: Compliant

2.3.8 Twisted-Pair Receiver
2.3.8.1 100 Mbits/s TP Receiver
2-18
Table 2.5
The device is capable of operating at either 10- or 100-Mbits/s. This
section describes the twisted-pair receivers and squelch operation for
both modes of operation.
The TP receiver detects input signals from the twisted-pair input and
converts them to a digital data bit stream ready for clock and data
recovery. The receiver can reliably detect 100BASE-TX compliant
transmitter data that has been passed through 0 to 100 meters of
100-ohm category 5 UTP or 150-ohm STP cable.
The 100 Mbits/s receiver consists of an adaptive equalizer, baseline
wander correction circuit, comparators, and an MLT3 decoder. The TP
inputs first go to an adaptive equalizer. The adaptive equalizer
compensates for the low-pass characteristics of the cable and can adapt
and compensate for 0 to 100 meters of category 5, 100-ohm or 150-ohm
STP cable. The baseline wander correction circuit restores the DC
component of the input waveform that the external transformers have
removed. The comparators convert the equalized signal back to digital
levels and qualify the data with the squelch circuit. The MLT3 decoder
Functional Description
Reference
W
M
O
Q
N
P
R
S
U
V
T
TP Output Voltage (10 Mbits/s) (Cont.)
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Time (ns) Internal MAU
100
110
111
108
111
110
100
110
58
85
90
Voltage (V)
0.15
0.75
1.0
0.4
0.15
1.0
0.3
0.7
0.7
0
0