L80227-LEADFREE LSI, L80227-LEADFREE Datasheet - Page 99

• Manufacturer Part Number: L80227-LEADFREE
• Manufacturer: LSI

Specifications of L80227-LEADFREE

• Lead Free Status / Rohs Status: Compliant

6.3.3 Receive Timing Characteristics
Table 6.8
Sym
t31
t32
t33
t34
t37
t38
t39
t40
Parameter
Start of Packet to
CRS Assert Delay
End of Packet to
CRS Deassert
Delay
Start of Packet to
RX_DV Assert
Delay
End of Packet to
RX_DV Deassert
Delay
RX_CLK to
RX_DV, RXD,
RX_ER Delay
RX_CLK High
Time
RX_CLK Low Time
SOI Pulse
Minimum Width
Required for Idle
Detection
Receive Timing
Table 6.8
through
AC Electrical Characteristics
Figure 6.8
Min
130
180
180
125
shows the Receive AC timing parameters. See
18
18
80
8
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Limit
for the receive timing diagrams.
Typ
200
200
20
20
3600
1000
Max
200
700
240
600
240
280
600
600
200
80
22
22
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
100 Mbits/s, MII
10 Mbits/s
100 Mbits/s, MII
10 Mbits/s. relative to start
of SOI pulse
100 Mbits/s
10 Mbits/s
100 Mbits/s
10 Mbits/s. relative to start
of SOI pulse
100 Mbits/s
10 Mbits/s
100 Mbits/s
10 Mbits/s
100 Mbits/s
10 Mbits/s
10 Mbits/s measure TPI
from last zero cross to
0.3 V point.
Figure 6.4
6-11