L80227-LEADFREE LSI, L80227-LEADFREE Datasheet - Page 63

• Manufacturer Part Number: L80227-LEADFREE
• Manufacturer: LSI

Specifications of L80227-LEADFREE

• Lead Free Status / Rohs Status: Compliant

3.5 Miscellaneous Signals
ANEG
COL
DPLX
NC
RESETn
Miscellaneous Signals
AutoNegotiation Input
This pin control AutoNegotiation operation.
Pin
HIGH
LOW
Collision Output
COL is asserted HIGH when a collision between transmit
and receive data is detected.
Full/Half Duplex Select Input
When the ANEG pin is LOW, the DPLX pin selects
Half/Full Duplex operation.
Pin
HIGH
LOW
When the ANEG pin is HIGH, the DPLX pin is ignored
and the Half/Full Duplex operation is controlled from the
Duplex Mode Select bit (DPLX) in the MI serial port Con-
trol register or the AutoNegotiation outcome.
No Connect
These pins are reserved for future use and should be left
floating for proper operation.
Hardware Reset Input
Pin
HIGH
LOW
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Meaning
AutoNegotiation is on.
AutoNegotiation Enable is controlled from the
ANEG_EN bit, 10/100 Mbits/s operation is controlled
from the SPEED bit, and Half/Full Duplex operation is
controlled from the DPLX bit.
AutoNegotiation is off.
10/100 Mbits/s operation is controlled from the SPEED
pin and Half/Full Duplex operation is controlled from the
DPLX pin.
Meaning
Full Duplex operation
Half Duplex operation
Meaning
Normal
Device in reset state. Reset is finished 100 ms after
RESETn goes HIGH.
Pullup I
3-7
O
I
I