LFX200EB-03FN256C Lattice, LFX200EB-03FN256C Datasheet - Page 15

• Manufacturer Part Number: LFX200EB-03FN256C
• Description: IC FPGA 200K GATES 256-BGA
• Manufacturer: Lattice

Specifications of LFX200EB-03FN256C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 11. ispXPGA PIO
VLI Routing Resources
The ispXPGA architecture contains a Variable-Length-Interconnect (VLI) routing technology connecting the PFUs,
PICs, and EBRs in the device. There are four types of routing resources, Global Lines, Long Lines, General Inter-
connect, and Local Lines forming the global routing structure. This allows a signal to be routed to any element in
the device with the optimal delay.
The Global Lines consist of global clock lines and a global set/reset line. These lines are routed to all elements in
the device. They are specifically designed for high speed, predictable timing regardless of fan-out. The global clock
lines can also be used as dedicated inputs.
The Long Lines consist of Horizontal and Vertical Long Lines (HLL and VLL). The VLL and HLL are tri-statable
lines spanning the entire device. These lines allow fast routing for high fan-out nets and general-purpose functions.
The General Interconnect consists of Double and Deca Lines. The Double Lines connect up to three elements (two
plus the driving element), while the Deca Lines connect up to eleven elements (ten plus the driving element).
The Local Lines are extremely fast routing paths consisting of Feedback and Direct Connect Lines. The Feedback
Lines are internal routing paths from the PFU outputs to the PFU inputs. The Direct Connect Lines connect all adja-
cent elements.
The Common Interface Block (CIB) provides the link between the logic element (PFU, PIC, or EBR) and the VLI
Routing resources. The CIB is a switch matrix that can be programmed to connect virtually any routing resource to
any input or output of the logic element.
Output Clock Enable (OCEN)
Input Clock Enable (ICEN)
PIO Output Enable(OEN)
Global Set/Reset(GSR)
Output Set/Reset (OSR)
PIO Input Enable (IEN)
Input Set/Reset (ISR)
From sysHSI block
From sysHSI block
Feed-through (FT)
From sysIO Input
PIO Input (IN)
Clock (CLK)
Only for PIOs associated with sysHSI Blocks
Delay
CLK/LE
CE
CE
CE
D
D
CLK/LE
D
CLK/LE
11
S R
S R
S R
Q
Q
Q
ispXPGA Family Data Sheet
To sysHSI
To sysHSI
To sysIO
To sysIO
To Routing
OE
Enable
Output
Output
OUT0
OUT1
block
block
Associated with
sysHSI Blocks
Only for PIOs