LFX200EB-03FN256C Lattice, LFX200EB-03FN256C Datasheet - Page 20

• Manufacturer Part Number: LFX200EB-03FN256C
• Description: IC FPGA 200K GATES 256-BGA
• Manufacturer: Lattice

Specifications of LFX200EB-03FN256C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-
faces includes different versions of SSTL and HSTL interfaces along with CTT, and GTL+. Usage of these particu-
lar I/O interfaces requires an additional V
Typically an output will be terminated to V
The third type of interface standards are the differential standards LVDS, BLVDS, and LVPECL. The differential
standards require two I/O pins to create the differential pair. The logic level is determined by the difference in the
two signals. Table 6 lists how these interface standards are implemented in the ispXPGA devices.
For more information on sysIO capability, refer to TN1000,
Figure 19. sysIO Banks per Device
Table 4. Number of I/Os per Bank
V
V
V
V
CCO0
GND
CCO1
GND
REF0
REF1
XPGA 1200
XPGA 500
XPGA 200
XPGA 125
I/O N
I/O N
I/O 0
I/O 0
Device
REF
TT
Bank 7
Bank 2
at the receiving end of the transmission line it is driving.
signal. At the system level a termination voltage, V
Max. Number of I/Os per Bank (N)
16
sysIO Usage Guidelines for Lattice
Bank 6
Bank 3
62
42
26
22
ispXPGA Family Data Sheet
I/O N
I/O N
I/O 0
I/O 0
V
V
GND
V
V
GND
CCO5
REF5
CCO4
REF4
Devices.
TT
, is also required.