LFX200EB-03FN256C Lattice, LFX200EB-03FN256C Datasheet - Page 5

• Manufacturer Part Number: LFX200EB-03FN256C
• Description: IC FPGA 200K GATES 256-BGA
• Manufacturer: Lattice

Specifications of LFX200EB-03FN256C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

February 2010
 Non-volatile, Infinitely Reconfigurable
 High Logic Density for System-level
 High Performance Programmable Function
 Flexible Memory Resources
 Flexible Programming, Reconfiguration,
Table 1. ispXPGA Family Selection Guide
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Functional Gates
PFUs
LUT-4s
Logic FFs
sysMEM Memory
Distributed Memory
EBR
sysHSI Channels
User I/O
Packaging
1. “E-Series” does not support sysHSI.
2. FH516 package was converted to F516 via
3. Discontinued via
Integration
Unit (PFU)
and Testing
• Instant-on - Powers up in microseconds via
• No external configuration memory
• Excellent design security, no bit stream to intercept
• Reconfigure SRAM based logic in milliseconds
• 139K to 1.25M functional gates
• 160 to 496 I/O
• 1.8V, 2.5V, and 3.3V V
• Up to 414Kb sysMEM™ embedded memory
• Four LUT-4 per PFU supports wide and narrow
• Dual flip-flops per LUT-4 for extensive pipelining
• Dedicated logic for adders, multipliers, multiplex-
• Multiple sysMEM Embedded RAM Blocks
• 64-bit distributed memory in each PFU
• Supports IEEE 1532 and 1149.1
on-chip E
functions
ers, and counters
– Single port, Dual port, and FIFO operation
– Single port, Double port, FIFO, and Shift
Register operation
1
2
PCN
CMOS
#03A-10.
®
based memory
CC
operation
PCN
ispXPGA 125/E
516 fpBGA
256 fpBGA
#09A-08.
160/176
139K
1936
3.8K
92K
30K
484
20
4
2
1
 Eight sysCLOCK™ Phase Locked Loops
 sysIO™ for High System Performance
 Two Options Available
 sysHSI™ Capability for Ultra Fast Serial
ispXPGA 200/E
516 fpBGA
256 fpBGA
(PLLs) for Clock Management
Communications
160/208
• Microprocessor configuration interface
• Program E
• True PLL technology
• 10MHz to 320MHz operation
• Clock multiplication and division
• Phase adjustment
• Shift clocks in 250ps steps
• High speed memory support through SSTL and
• Advanced buses supported through PCI, GTL+,
• Standard logic supported through LVTTL,
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
• Programmable drive strength for series termination
• Programmable bus maintenance
• High-performance sysHSI (standard part number)
• Low-cost, no sysHSI (“E-Series”)
• Up to 800Mbps performance
• Up to 20 channels per device
• Built in Clock Data Recovery (CDR) and
210K
111K
2704
5.4K
43K
676
24
HSTL
LVDS, BLVDS, and LVPECL
LVCMOS 3.3, 2.5 and 1.8
interfaces
Serialization and De-serialization (SERDES)
8
2
ispXPGA Family
2
CMOS while operating from SRAM
ispXPGA 500/E
516 fpBGA
900 fpBGA
14.1K
476K
1764
7056
184K
112K
336
40
12
2
®
Data Sheet DS1026
ispXPGA 1200/E
680 fpSBGA
900 fpBGA
DS1026_15.0
1.25M
15376
30.7K
414K
246K
3844
496
90
20
3