LFE3-150EA-8FN672C Lattice, LFE3-150EA-8FN672C Datasheet - Page 109
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LFE3-150EA-8FN672C
Manufacturer Part Number
LFE3-150EA-8FN672C
Description
IC FPGA 149KLUTS 380I/O 672-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-150EA-8FN672C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 3-24. Power-On-Reset (POR) Timing
Figure 3-25. sysCONFIG Port Timing
PROGRAMN
DONE
DOUT
CCLK
INITN
sysIO
VCC
DI
V
V
1. Time taken from V
2. Device is in a Master Mode (SPI, SPIm).
3. The CFG pins are normally static (hard wired).
CC
CCIO8
CFG[2:0]
/ V
t
ICFG
DONE
CCLK
CCAUX
1
INITN
t
DPPDONE
2
3
t
IODISS
/
t
t
PRGM
PRGMRJ
t
t
VMC
DINIT
CC
, V
CCAUX
t
DPPINIT
t
t
or V
HSCDI
SUSCDI
CCIO8
(t
(t
HMCDI
SUMCDI
, whichever is the last to cross the POR trip point.
t
ICFG
)
)
t
VMC
3-56
Valid
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
t
t
t
SSCH
SSCL
CODO
Wake Up Clocks
t
IOENSS
GOE Release
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