LFE3-150EA-8FN672C Lattice, LFE3-150EA-8FN672C Datasheet - Page 74
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LFE3-150EA-8FN672C
Manufacturer Part Number
LFE3-150EA-8FN672C
Description
IC FPGA 149KLUTS 380I/O 672-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-150EA-8FN672C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-8FN672C
Manufacturer:
ST
Quantity:
1 200
Company:
Part Number:
LFE3-150EA-8FN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFE3-150EA-8FN672C
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
LFE3-150EA-8FN672CTW
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
LatticeECP3 External Switching Characteristics (Continued)
f
t
t
f
Generic DDRX2 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX2_RX.DQS.Centered) Using DQS
Pin for Clock Input
Left and Right Sides
t
t
f
Generic DDRX2 Inputs with Clock and Data (<10 Bits Wide) Aligned at Pin (GDDRX2_RX.DQS.Aligned) Using DQS Pin
for Clock Input
Left and Right Sides
t
t
f
Generic DDRX1 Output with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX1_TX.SCLK.Centered)
t
t
f
t
t
f
t
t
f
t
t
f
Generic DDRX1 Output with Clock and Data Aligned at Pin (GDDRX1_TX.SCLK.Aligned)
t
t
f
t
t
f
t
t
f
t
t
f
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
DIBGDDR
DIAGDDR
MAX_GDDR
DIBGDDR
DIAGDDR
MAX_GDDR
DIBGDDR
DIAGDDR
MAX_GDDR
DIBGDDR
DIAGDDR
MAX_GDDR
Parameter
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Valid Before CLK
Data Valid After CLK
DDRX1 Clock Frequency
Data Valid Before CLK
Data Valid After CLK
DDRX1 Clock Frequency
Data Valid Before CLK
Data Valid After CLK
DDRX1 Clock Frequency
Data Valid Before CLK
Data Valid After CLK
DDRX1 Clock Frequency
Data Invalid Before Clock
Data Invalid After Clock
DDRX1 Clock Frequency
Data Invalid Before Clock
Data Invalid After Clock
DDRX1 Clock Frequency
Data Invalid Before Clock
Data Invalid After Clock
DDRX1 Clock Frequency
Data Invalid Before Clock
Data Invalid After Clock
DDRX1 Clock Frequency
Over Recommended Commercial Operating Conditions
Description
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
All ECP3EA Devices 330
All ECP3EA Devices 330
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices 0.775
All ECP3EA Devices
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
3-21
Device
DC and Switching Characteristics
0.790
Min. Max. Min. Max. Min. Max.
670
670
666
666
683
683
683
683
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
-8
0.210
0.225
235
235
400
400
250
250
250
250
335
335
250
339
339
250
322
322
250
322
322
250
—
—
—
—
—
—
—
—
—
—
—
—
0.790
0.775
330
330
670
670
665
665
688
688
688
688
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
0.210
0.225
1, 2
170
170
400
400
250
250
250
250
338
338
250
343
343
250
320
320
250
320
320
250
—
—
—
—
—
—
—
—
—
—
—
—
0.790
0.775
352
352
670
670
664
664
690
690
690
690
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
0.210
0.225
130
130
375
375
10
250
250
250
250
341
341
250
347
347
250
321
321
250
321
321
250
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
UI
UI
ps
ps
UI
UI
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps