MT48H8M16LFB4-75 IT:KTR Micron Technology Inc, MT48H8M16LFB4-75 IT:KTR Datasheet - Page 22

• Manufacturer Part Number: MT48H8M16LFB4-75 IT:KTR
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-75 IT:KTR

• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
10. For auto precharge mode, the precharge timing budget (
11. CLK must be toggled a minimum of two times during this period.
12. Required clocks are specified by JEDEC functionality and are not dependent on any tim-
13. Timing is specified by
14. Timing is specified by
15. Timing is specified by
16. Based on
9. AC characteristics assume
timing must be derated. Input setup times require an additional 50ps for each 100 mV/
ns reduction in slew rate. Input hold times remain unchanged. If the slew rate exceeds
4.5V/ns, functionality is uncertain.
after the first clock delay and after the last WRITE is executed.
ing parameter.
cycle rate.
t
CK (MIN), CL = 3.
Electrical Specifications – AC Operating Conditions
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
t
t
t
CKS. Clock(s) specified as a reference only at minimum cycle rate.
WR plus
WR.
22
t
T = 1ns. For command and address input slew rates <0.5V/ns,
t
RP. Clock(s) specified as a reference only at minimum
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP) begins at
©2008 Micron Technology, Inc. All rights reserved.
t
RP – (1 ×
t
CKns),