PCF8576DT NXP Semiconductors, PCF8576DT Datasheet - Page 32

• Manufacturer Part Number: PCF8576DT
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT

• Operating Supply Voltage (typ): 2.5/3.3/5V
• Number Of Digits: 20
• Number Of Segments: 160
• Package Type: TSSOP
• Pin Count: 56
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Frequency (max): 400KHz
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
12. Application information
PCF8576D_9
Product data sheet
12.1 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can be differentiated on the same
I
programmable I
Table 17.
PCF8576Ds connected in cascade are synchronized to allow the backplane signals from
only one device in the cascade to be shared. This arrangement is cost-effective in large
LCD applications since the backplane outputs of only one device need to be
through-plated to the backplane electrodes of the display. The other cascaded
PCF8576Ds contribute additional segment outputs but their backplane outputs are left
open-circuit (see
All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal.
This synchronization is guaranteed after the power-on reset. The only time that SYNC is
likely to be needed is if synchronization is lost accidentally, for example, by noise in
adverse electrical environments, or if the LCD multiplex drive mode is changed in an
application using several cascaded PCF8576Ds, as the drive mode cannot be changed on
all of the cascaded devices simultaneously. SYNC can be either an input or an output
signal; a SYNC output is implemented as an open-drain driver with an internal pull-up
resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and
monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored
by the first PCF8576D to assert SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for each LCD drive mode is shown in
Cluster
1
2
2
C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the
Addressing cascaded PCF8576D
Bit SA0
0
1
2
C-bus slave address (SA0).
Figure
Rev. 09 — 25 August 2009
22).
Pin A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Universal LCD driver for low multiplex rates
Pin A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Pin A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PCF8576D
Figure
© NXP B.V. 2009. All rights reserved.
Device
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
23.
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