MC68HC705C8ACB Freescale Semiconductor, MC68HC705C8ACB Datasheet - Page 82

• Manufacturer Part Number: MC68HC705C8ACB
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705C8ACB

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 2.1MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 304Byte
• # I/os (max): 24
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Not Compliant

Parallel Input/Output (I/O)
7.4.2 Data Direction Register B
Technical Data
82
NOTE:
Address:
The contents of data direction register B (DDRB) shown in
determine whether each port B pin is an input or an output. Writing a
logic 1 to a DDRB bit enables the output buffer for the associated port B
pin; a logic 0 disables the output buffer. A reset clears all DDRB bits,
configuring all port B pins as inputs. If the pullup devices are enabled by
mask option, setting a DDRB bit to a logic 1 turns off the pullup device
for that pin.
DDRB7–DDRB0 — Port B Data Direction Bits
Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
Reset:
Read:
Write:
These read/write bits control port B data direction. Reset clears bits
DDRB7–DDRB0.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
DDRB7
$0005
Bit 7
0
Figure 7-5. Data Direction Register B (DDRB)
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Parallel Input/Output (I/O)
DDRB6
6
0
DDRB5
5
0
DDRB4
4
0
DDRB3
3
0
DDRB2
MC68HC705C8A — Rev. 3
2
0
DDRB1
1
0
Figure 7-5
DDRB0
Bit 0
0