LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 13

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

4.6 Byte Write Command
Byte write is executed by a two-cycle command sequence.
Byte write setup (standard 40H or alternate 10H) is
written, followed by a second write that specifies the
address and data (latched on the rising edge of WE#). The
WSM then takes over, controlling the byte write and write
verify algorithms internally. After the byte write sequence
is written, the device automatically outputs status register
data when read (see Figure 6). The CPU can detect the
completion of the byte write event by analyzing the status
register bit SR.7.
When byte write is complete, status register bit SR.4
should be checked. If byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
Reliable byte writes can only occur when V
and V
memory contents are protected against byte writes. If byte
write is attempted while V
SR.3 and SR.4 will be set to "1". Successful byte write for
boot blocks requires that the corresponding if set, that
WP#=V
block when the corresponding WP#=V
SR.1 and SR.4 will be set to "1". Byte write operations
with V
not be attempted.
PP
IH
IH
=V
<RP#<V
or RP#=V
PPH1/2/3
HH
. In the absence of this high voltage,
HH
produce spurious results and should
. If byte write is attempted to boot
PP
V
PPLK
, status register bits
IL
CC
or RP#=V
=2.7V-3.6V
IH
,
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block-erase
interruption to read or byte write data in another block of
memory. Once the block-erase process starts, writing the
Block Erase Suspend command requests that the WSM
suspend the block erase sequence at a predetermined point
in the algorithm. The device outputs status register data
when read after the Block Erase Suspend command is
written. Polling status register bits SR.7 and SR.6 can
determine when the block erase operation has been
suspended (both will be set to "1"). Specification section
6.2.8 defines the block erase suspend latency.
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Byte Write Suspend command (see Section 4.8),
a byte write operation can also be suspended. During a
byte write operation with block erase suspended, status
register bit SR.7 will return to "0". However, SR.6 will
remain "1" to indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear. After the Erase Resume command is
written, the device automatically outputs status register
data when read (see Figure 7). V
V
block erase is suspended. RP# must also remain at V
V
also remain at V
block erase). Block erase cannot resume until byte write
operations initiated during block erase suspend have
completed.
PPH1/2/3
HH
(the same RP# level used for block erase). WP# must
(the same V
IL
or V
PP
IH
level used for block erase) while
(the same WP# level used for
PP
must remain at
Rev. 1.1
IH
or