LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 7

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

DQ
Symbol
A
GND
WE#
WP#
CE#
OE#
V
RP#
0
V
NC
0
-A
-DQ
CC
PP
19
7
OUTPUT
SUPPLY
SUPPLY
SUPPLY GROUND: Do not float any ground pins.
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data
during memory array, status register and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched during a
write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal
automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations
which provides data protection during power transitions. Exit from deep power-down sets the
device to read array mode. With RP#=V
without WP# state. Block erase or byte write with V
should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
WRITE PROTECT: Master control for boot blocks locking. When V
be erased and programmed.
BLOCK ERASE AND BYTE WRITE POWER SUPPLY: For erasing array blocks or writing
bytes. With V
invalid V
DEVICE POWER SUPPLY: Do not float any power pins. With V
the flash memory are inhibited. Device operations at invalid V
produce spurious results and should not be attempted.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
16
-A
19
PP
: Main Block Address. (Boot and Parameter block Addresses are A
(see DC Characteristics) produce spurious results and should not be attempted.
PP
V
PPLK
Table 2. Pin Descriptions
, memory contents cannot be altered. Block erase and byte write with an
Name and Function
HH
, block erase or byte write can operate to all blocks
IH
<RP#<V
CC
HH
voltage (see DC Characteristics)
CC
produce spurious results and
IL
V
, locked boot blocks cannot
LKO
, all write attempts to
13
-A
19
.)
Rev. 1.1