LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 21

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

5.5 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure or byte writing during power
transitions. Upon power-up, the device is indifferent as to
which power supply (V
Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious writes for
V
WE# and CE# must be low for a command write, driving
either to V
command sequence architecture provides added level of
protection against data alteration.
WP# provide additional protection from inadvertent code
or data alteration. The device is disabled while RP#=V
regardless of its control inputs state.
CC
voltages above V
IH
will inhibit writes. The CUI’s two-step
LKO
PP
when V
or V
PP
CC
is active. Since both
) powers-up first.
IL
5.6 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
In addition, deep power-down mode ensures extremely
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
power by lowering RP# to V
access is again needed, the devices can be read following
the t
first raised to V
and Write Operations and Figures 11, 12 and 13 for more
information.
PHQV
and t
PHWL
IH
. See AC Characteristics− Read Only
wake-up cycles required after RP# is
IL
standby or sleep modes. If
Rev. 1.1