LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 5

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

1 INTRODUCTION
This datasheet contains LH28F008BVT-BTL10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F008BVT-BTL10 Smart3
Flash memory are:
Please note following important differences:
1.2 Product Overview
The LH28F008BVT-BTL10 is a high-performance 8-Mbit
Smart3 Flash memory organized as 1M-byte of 8 bits.
The 1M-byte of data is arranged in two 8K-byte boot
blocks, six 8K-byte parameter blocks and fifteen 64K-byte
main blocks which are individually erasable in-system.
The memory map is shown in Figure 3.
Smart3 technology provides a choice of V
combinations, as shown in Table 1, to meet system
performance and power expectations. V
and 4.5V-5.5V eliminates the need for a separate 12V
converter, while V
byte write performance. In addition to flexible erase and
program voltages, the dedicated V
data protection when V
Table 1. V
V
Smart3 Technology
Enhanced Suspend Capabilities
Boot Block Architecture
V
and 4.5V-5.5V block erase and byte write operations.
The V
for designs that switch V
To take advantage of Smart3 technology, allow V
and V
2.7V-3.6V
CC
PPLK
Voltage
PP
PP
has been lowered to 1.5V to support 2.7V-3.6V
CC
connection to 2.7V-3.6V.
voltage transitions to GND is recommended
and V
Smart3 Technology
2.7V-3.6V, 4.5V-5.5V, 11.4V-12.6V
PP
PP
=12V maximizes block erase and
PP
Voltage Combinations Offered by
PP
V
PPLK
off during read operation.
V
PP
.
PP
Voltage
pin gives complete
PP
at 2.7V-3.6V
CC
and V
CC
PP
Internal V
configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and byte write
operations.
A block erase operation erases one of the device’s 64K-
byte blocks typically within 0.51s (2.7V-3.6V V
11.4V-12.6V V
(2.7V-3.6V V
blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software
to suspend block erase to read or write data from any other
block.
Writing memory data is performed in byte increments of
the device’s 64K-byte blocks typically within 12.6µs
(2.7V-3.6V V
typically within 24.5µs (2.7V-3.6V V
V
data or execute code from any other flash memory array
location.
The boot blocks can be locked for the WP# pin. Block
erase or byte write for boot block must not be carried out
by WP# to Low and RP# to V
The status register indicates when the WSM’s block erase
or byte write operation is finished.
The access time is 100ns (t
temperature range (0°C to +70°C) and V
range of 2.7V-3.6V.
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical I
current is 3mA at 2.7V V
When CE# and RP# pins are at V
standby mode is enabled. When the RP# pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during
reset. A reset time (t
high until outputs are valid. Likewise, the device has a
wake time (t
are recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 40-lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in Figure
2.
PP
). Byte write suspend mode enables the system to read
CC
PHEL
CC
and V
CC
PP
, 11.4V-12.6V V
, 11.4V-12.6V V
), 8K-byte blocks typically within 0.31s
) from RP#-high until writes to the CUI
PHQV
PP
detection Circuitry automatically
CC
) is required from RP# switching
.
AVQV
IH
.
PP
) over the commercial
) independent of other
PP
CC
), 8K-byte blocks
, the I
CC
CC
, 11.4V-12.6V
supply voltage
CC
Rev. 1.1
CMOS
CCR
CC
,