S29GL032M10TAIR10 AMD (ADVANCED MICRO DEVICES), S29GL032M10TAIR10 Datasheet - Page 58

• Manufacturer Part Number: S29GL032M10TAIR10
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of S29GL032M10TAIR10

• Lead Free Status / Rohs Status: Not Compliant

Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory
Write Protect (WP#)
Hardware Data Protection
56
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from
the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked
device has an 16-byte random ESN at addresses 000000h–000007h. Please contact your sales
representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion pro-
gramming service (Customer Factory Locked). The devices are then shipped from the factory with
the Secured Silicon Sector permanently locked. Contact your sales representative for details on
using the Spansion programming service.
The Write Protect function provides a hardware method of protecting the first or last sector group
without using V
If the system asserts V
in the first or last sector group independently of whether those sector groups were protected or
unprotected. Note that if WP#/ACC is at V
mum input load current is increased
Note: If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously
set to be protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that
WP# has an internal pullup; when unconnected, WP# is at VIH.
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes
dition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during V
power-up and power-down transitions, or from system noise.
Low V
When V
V
disabled, and the device resets to the read mode. Subsequent writes are ignored until V
greater than V
intentional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
the rising edge of WE#. The internal state machine is automatically reset to the read mode on
power-up.
CC
power-up and power-down. The command register and all internal program/erase circuits are
CC
CC
is less than V
Write Inhibit
LKO
ID
. Write Protect is one of two functions provided by the WP#/ACC input.
. The system must provide the proper signals to the control pins to prevent un-
IL
and OE# = V
IL
LKO
S29GL-M MirrorBit
on the WP#/ACC pin, the device disables program and erase functions
CC
, the device does not accept any write cycles. This protects data during
is greater than V
IH
during power up, the device does not accept commands on
(Table
(Table 34
D a t a
TM
IL
29).
Flash Family
when the device is in the standby mode, the maxi-
LKO
and
S h e e t
.
Table 35
IL
, CE# = V
contain command definitions). In ad-
IH
or WE# = V
S29GL-M_00_B8 February 7, 2007
IH
. To initiate
CC
CC
is