XPC850ZT50B Freescale Semiconductor, XPC850ZT50B Datasheet - Page 36

XPC850ZT50B

Manufacturer Part Number
XPC850ZT50B
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XPC850ZT50B

Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 95C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
BGA
Lead Free Status / Rohs Status
Not Compliant

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Layout Practices
1
Figure 6-24 provides the PCMCIA access cycle timing for the external bus read.
36
Num
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.
CLKOUT to ALE negate time
PCWE, IOWR negated to D[0–31]
invalid.
WAIT_B valid to CLKOUT rising edge.
CLKOUT rising edge to WAIT_B invalid.
Figure 6-24. PCMCIA Access Cycles Timing External Bus Read
1
Characteristic
Freescale Semiconductor, Inc.
Table 6-8. PCMCIA Timing (continued)
MPC850 (Rev. A/B/C) Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
1
1
3.00
8.00
2.00
Min
50MHz
13.00
Max
6.00
8.00
2.00
Min
66MHz
16.00
Max
4.00
8.00
2.00
Min
80 MHz
14.00
Max
FFACTOR Unit
0.250
0.250
MOTOROLA
ns
ns
ns
ns

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