M24256-AWMN6T STMicroelectronics, M24256-AWMN6T Datasheet - Page 4

• Manufacturer Part Number: M24256-AWMN6T
• Manufacturer: STMicroelectronics

Specifications of M24256-AWMN6T

• Density: 256Kb
• Interface Type: Serial (I2C)
• Organization: 32Kx8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC N
• Operating Temp Range: -40C to 85C
• Supply Current: 1mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

M24256-A
Figure 4. I
unconnected, the WC input is internally read as
V
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001 . Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
4/20
IL
, and write operations are allowed.
SCL
SDA
SCL
SDA
SCL
SDA
2
C Bus Protocol
Condition
START
MSB
Condition
START
1
MSB
1
2
2
C protocol.
2
Input
SDA
3
3
Change
SDA
device is always a slave device in all communica-
tion.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
7
7
8
8
ACK
9
Condition
ACK
STOP
9
Condition
STOP
AI00792B