M24256-AWMN6T STMicroelectronics, M24256-AWMN6T Datasheet - Page 7

• Manufacturer Part Number: M24256-AWMN6T
• Manufacturer: STMicroelectronics

Specifications of M24256-AWMN6T

• Density: 256Kb
• Interface Type: Serial (I2C)
• Organization: 32Kx8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC N
• Operating Temp Range: -40C to 85C
• Supply Current: 1mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

Figure 6. Write Mode Sequences with WC=0 (data write enabled)
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
w
) is shown in Table 9, but the
DEV SEL
DEV SEL
ACK
DATA IN N
R/W
R/W
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
ACK
ACK
– Step 2: if the memory is busy with the internal
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the mas-
ter sends another START condition, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
BYTE ADDR
BYTE ADDR
write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-
minated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
ACK
ACK
DATA IN 1
DATA IN
ACK
ACK
DATA IN 2
AI01106B
M24256-A
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