M24256-AWMN6T STMicroelectronics, M24256-AWMN6T Datasheet - Page 5

• Manufacturer Part Number: M24256-AWMN6T
• Manufacturer: STMicroelectronics

Specifications of M24256-AWMN6T

• Density: 256Kb
• Interface Type: Serial (I2C)
• Organization: 32Kx8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC N
• Operating Temp Range: -40C to 85C
• Supply Current: 1mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

Table 3. Device Select Code
Note: 1. The most significant bit, b7, is sent first.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (0, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Up to four memory devices can be connected on a
single I
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the mem-
ory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
Table 6. Operating Modes
Note: 1. X =
Device Select Code
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
2
C bus. Each one is given a unique 2-bit
V
Mode
IH
or V
IL
.
b7
1
Device Type Identifier
RW bit
1
1
0
1
1
0
0
b6
0
th
WC
V
V
clock
b5
X
X
X
X
1
IL
IL
1
Data Bytes
Table 4. Most Significant Byte
Note: 1. b15 is treated as Don’t Care on the M24256-A series.
Table 5. Least Significant Byte
The 8
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4) is sent first, followed by the Least significant
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as Don’t
Care bits on the M24256-A memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re-
b4
b15
b7
0
1
1
1
64
1
th
b14
b6
bit is the RW bit. This is set to ‘1’ for read
th
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
START, Device Select, RW = 0
bit time. If the memory does not match
b3
0
b13
b5
Chip Enable
b12
b4
Initial Sequence
E1
b2
b11
b3
E0
b10
b2
b1
M24256-A
b9
b1
RW
RW
b0
b8
b0
5/20