N28F001BXT150 Intel, N28F001BXT150 Datasheet - Page 12

• Manufacturer Part Number: N28F001BXT150
• Manufacturer: Intel

Specifications of N28F001BXT150

• Density: 1Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 17b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

28F001BX
3.1
The 28F001BX has three read modes. The memory
can be read from any of its blocks, and information
can be read from the intelligent identifier or the
status register. V
The first task is to write the appropriate Read Mode
command
intelligent
28F001BX automatically resets to read array mode
upon initial device power-up or after exit from deep
power-down. The 28F001BX has four control pins,
two of which must be logically active to obtain data
at the outputs. Chip Enable (CE#) is the device
selection control, and when active enables the
selected memory device. Output Enable (OE#) is
the data input/output (DQ
and when active drives data from the selected
memory onto the I/O bus. RP# and WE# must also
be at V
waveforms.
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
12
Read
Output Disable
Standby
Deep Power Down
Intelligent Identifier
(Mfr)
Intelligent Identifier
(Device)
Write
Refer to Section 10.4, DC Characteristics . When V
erased.
X can be V
See DC Characteristics , for V
Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. A
A
Device ID = 94H for the 28F001BX-T and 95H for the 28F001BX-B.
Command writes involving block erase or byte program are successfully executed only when V
Refer to Table 3 for valid D
Program or erase the boot block by holding RP# at V
operations.
10
–A
Mode
IH
16
Read
. Figure 11 illustrates read bus cycle
= V
identifier,
to
IL
IL
or V
.
PP
the
IH
can be at either V
2, 3, 4, 5
2, 6, 7, 8
for control pins and addresses, and V
1, 2, 3
2, 3, 4
Notes
command
or
2
2
2
0
IN
–DQ
status
during a write operation.
PPL
7
, V
RP#
) direction control,
V
V
V
V
V
V
V
PPH
IH
IH
IH
IH
IH
IH
IL
register
Table 2. 28F001BX Bus Operations
register).
, V
PPL
HH
or V
and V
CE#
V
V
V
V
V
V
X
IH
IL
IL
IL
IL
IL
(array,
PPH
ID
PP
The
.
voltages.
HH
= V
or toggling OE# to V
OE#
PPL
PPL
V
V
V
V
V
X
X
IH
IH
IL
IL
IL
, memory contents can be read but not programmed or
or V
3.2
With OE# at a logic-high level (V
outputs are disabled. Output pins (DQ
placed in a high-impedance state.
3.3
CE# at a logic-high level (V
in standby mode. Standby operation disables much
of the 28F001BX’s circuitry and substantially
reduces device power consumption. The outputs
(DQ
independent of the status of OE#. If the 28F001BX
is deselected during erase or program, the device
will continue functioning and consuming normal
active power until the operation is completed.
PPH
0
WE#
–DQ
for V
V
V
V
V
V
X
X
IH
IH
IH
IH
IL
Output Disable
Standby
7
PP
) are placed in a high-impedance state
.
HH
. See AC waveforms for program/erase
V
V
A
X
X
X
X
X
ID
ID
9
V
V
A
X
X
X
X
X
IL
IH
IH
0
PP
) places the 28F001BX
= V
PPH
V
.
X
X
X
X
X
X
X
IH
PP
), the device
0
–DQ
High Z
High Z
High Z
DQ
D
94H,
89H
95H
D
1
7
OUT
–A
) are
IN
0–7
8
,