N28F001BXT150 Intel, N28F001BXT150 Datasheet - Page 22

• Manufacturer Part Number: N28F001BXT150
• Manufacturer: Intel

Specifications of N28F001BXT150

• Density: 1Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 17b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

28F001BX
9.0 DESIGN CONSIDERATIONS
Flash memories are often used in larger memory
arrays. Intel provides three control inputs to
accommodate multiple memory connections. Three-
line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention
To efficiently use these control inputs, an address
decoder should enable CE#, while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory
deselected memory devices are in standby mode.
RP#
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
9.1
Flash memory power switching characteristics
require careful device coupling. System designers
are interested in three supply current issues;
standby current levels (I
(I
rising edges of CE#. Transient current magnitudes
depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper
decoupling
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its
V
These high frequency, low inherent-inductance
capacitors should be placed as close as possible to
the device. Additionally, for every eight devices, a
4.7 µF electrolytic capacitor should be placed at the
array’s power supply connection between V
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductances.
9.2
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V
supply trace. The V
current for programming. Use similar trace widths
and layout considerations given to the V
22
CC
CC
) and transient peaks producted by falling and
will not occur
and GND, and between its V
should
Power Supply Decoupling
V
Boards
devices
PP
capacitor
Trace on Printed Circuit
be
PP
have
connected
pin supplies the memory cell
selection
SB
), active current levels
active
to
outputs
will
PP
the
and GND.
PP
CC
suppress
system
CC
power
power
while
and
bus. Adequate V
will decrease V
9.3
Programming and erase completion are
guaranteed if V
status bit of the status register (SR.3) is set to “1”, a
Clear Status Register command must be issued
before further program/erase attempts are allowed
by the WSM. Otherwise, the program (SR.4) or
erase (SR.5) status bits of the status register will be
set to “1” if error is detected. RP# transitions to V
during program and erase also abort the operations.
Data is partially altered in either case, and the
command sequence must be repeated after normal
operation is restored. Device power-off, or RP#
transitions to V
value 80H.
The command register latches commands as
issued by system software and is not altered by V
or CE# transitions or WSM actions. Its state upon
power-up, after exit from deep power-down or after
V
mode.
After program or erase is complete, even after V
transitions down to V
must be reset to read array mode via the Read
Array command if access to the memory array is
desired.
9.4
The 28F001BX is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power-up, the 28F001BX is
indifferent as to which power supply, V
powers up first. Power supply sequencing is not
required. Internal circuitry in the 28F001BX ensures
that the command register is reset to read array
mode on power-up.
A system designer must guard against spurious
writes for V
active. Since both WE# and CE# must be low for a
command write, driving either to V
writes. The command register architecture provides
an added level of protection since alteration of
memory contents only occurs after successful
completion of the two-step command sequences.
CC
transitions below V
V
the Command/Status Registers
Power-Up/Down Protection
CC
CC
, V
PP
IL
voltages above V
PP
, clear the status register to initial
PP
voltage spikes and overshoots.
PP
drops below V
, RP# Transitions and
supply traces and decoupling
PPL
LKO
, the command register
, is FFH, or read array
LKO
PPH
IH
when V
. If the V
PP
will inhibit
or V
PP
not
CC
PP
PP
PP
is
IL
,