ACS8510 Semtech, ACS8510 Datasheet - Page 45

• Manufacturer Part Number: ACS8510
• Manufacturer: Semtech

Specifications of ACS8510

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

Alignment of the Selection of Reference Sources
Alignment of the Selection of Reference Sources
for T
for T
A C S 8 5 1 0
A C S 8 5 1 0
Alignment of the Phases of the 8kHz and 2kHz
Alignment of the Phases of the 8kHz and 2kHz
Clocks in both Master and Slave ACS8510
Clocks in both Master and Slave ACS8510
Alignment of the Selection of Reference Sources
Alignment of the Selection of Reference Sources
Alignment of the Selection of Reference Sources
for T
for T
for T
A C S 8 5 1 0
A C S 8 5 1 0
A C S 8 5 1 0
As stated previously, there is no need to align
the phases of the T
Slave devices. There is a need, however, to
ensure that all devices select the same
reference source. But, since there is no
Holdover mode required for the generation of
the T
continuously monitored within each device, it is
permissible to rely on external intelligence to
command a switch-over to an alternative source
should the selected one fail. The time delay
involved in detecting the failure, indicating it to
the outside and selecting a new source, will
result only in the SSU/BITS entering its Holdover
mode for a short time.
Alignment of the Phases of the 8kHz and 2kHz
Alignment of the Phases of the 8kHz and 2kHz
Alignment of the Phases of the 8kHz and 2kHz
Clocks in both Master and Slave ACS8510
Clocks in both Master and Slave ACS8510
Clocks in both Master and Slave ACS8510
In addition to aligning the edges of the T
outputs of Master and Slave devices, it is
necessary to align the edges of the Frame and
Multi-Frame clocks. If this is not performed,
frame alignment may be lost in distant
equipment on switch-over to an alternative
device, resulting in anomalous network
operation of a very serious nature.
In accordance with the alignment mechanism
used with the main T
opening paragraphs of this section), whereby
the 6.48 MHz output of the Master device is
supplied to the Slave device, the alignment of
both the 8 kHz and 2 kHz clocks is
accomplished (they are already synchronous to
the T
the Master device into the Slave device. The
Multi-Frame Sync clock output of the Slave
device is also fed to the Sync2K input of the
Master device. Alignment of the Multi-Frame
Sync input occurs only when cnfg_mode
register, bit 3, address 34Hex External 2 kHz
Sync Enable is set to 1.
Revision 2.00/September 2003
ADVANCED COMMUNICATIONS
OUT4
OUT4
OUT4
OUT4
OUT4
OUT0
OUT4
clocks) by feeding the 2 kHz clock of
Generation in the Master and Slave
Generation in the Master and Slave
Generation in the Master and Slave
clock, and every reference source is
Generation in the Master and Slave
Generation in the Master and Slave
OUT4
OUT0
outputs in Master and
clock (described in the
Semtech Corp.
OUT0
45
J T A G
J T A G
J T A G
J T A G
J T A G
The JTAG connections on the ACS8510 allow a
full boundary scan to be made. The JTAG
implementation is fully compliant to IEEE
1149.1, with the following minor exceptions,
and the user should refer to the standard for
further information.
1. The output boundary scan cells do not capture data
from the core, and so do not support EXTEST. However
this does not affect board testing.
2. In common with some other manufacturers, pin TRST
is internally pulled low to disable JTAG by default. The
standard is to pull high. The polarity of TRST is as the
standard: TRST high to enable JTAG boundary scan mode,
TRST low for normal operation.
3. The device does not support the optional tri-state
capability (HIGHZ). This will be supported on the next
revision of the device.
The JTAG timing diagram is shown in Figure 17.
P O R B
P O R B
P O R B
P O R B
P O R B
The Power On Reset (PORB) pin resets the
device if forced Low for a power on reset to be
initiated. The reset is asynchronous, the
minimum Low pulse width is 5 ns. Reset is
needed to initialize all of the register values to
their defaults. Asserting Reset is required at
power on, and may be re-asserted at any time
to restore defaults. This is implemented most
simplistically by an external capacitor to GND
along with the internal pull-up resistor. The
ACS8510 is held in a reset state for 250 ms
after the PORB pin has been pulled High. In
normal operation PORB should be held High.
ACS8510 Rev2.1 SETS
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FINAL