ACS8510 Semtech, ACS8510 Datasheet - Page 69

• Manufacturer Part Number: ACS8510
• Manufacturer: Semtech

Specifications of ACS8510

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

Serial Mode
Serial Mode
Serial Mode
Serial Mode
Serial Mode
In Serial mode, the device is configured to interface with a serial microprocessor bus.The combined minimum
High and Low times for SCLK define the maximum clock rate.
For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is
affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us).
This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read
mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final
address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With
CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock
out the SDO.
A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking
it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has
a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz.
SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing
diagrams for Write and Read access for this mode.
Figure 25. Read Access Timing in Serial Mode
Figure 25. Read Access Timing in Serial Mode
Figure 25. Read Access Timing in Serial Mode
Figure 25. Read Access Timing in Serial Mode
Figure 25. Read Access Timing in Serial Mode
Revision 2.00/September 2003
ADVANCED COMMUNICATIONS
CSB
SCLK
SDI
SDO
CSB
SCLK
SDI
SDO
t
su1
CLKE = 0; SDO data is clocked out on the rising edge of SCLK
CLKE = 1; SDO data is clocked out on the falling edge of SCLK
t
su2
Output not driven, pulled low by internal resistor
Output not driven, pulled low by internal resistor
R/W
R/W
_
_
Semtech Corp.
A0 A1 A2 A3 A4 A5 A6
A0 A1 A2 A3 A4 A5 A6
t
h1
t
pw1
t
pw2
69
ACS8510 Rev2.1 SETS
D0 D1 D2 D3 D4 D5 D6 D7
t
d1
D0 D1 D2 D3 D4 D5 D6 D7
t
d1
F8525D_013ReadAccSerial_01
t
h2
t
www.semtech.com
h2
t
d2
t
d2
FINAL