S29GL256M10TAIR10 Spansion Inc., S29GL256M10TAIR10 Datasheet - Page 26

• Manufacturer Part Number: S29GL256M10TAIR10
• Manufacturer: Spansion Inc.

Specifications of S29GL256M10TAIR10

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3/11.5 to 12.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
24
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V
± 0.3 V. (Note that this is a more restricted voltage range than V
at V
greater. The device requires standard access time (t
ther of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
See
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for t
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
available to the system. See
specification.
The RESET# pin provides a hardware method of resetting the device to reading array data. When
the RESET# pin is driven low for at least a period of t
operation in progress, tristates all output pins, and ignores all read/write commands for the du-
ration of the RESET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
device draws CMOS standby current (I
standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
See
When the OE# input is at V
the high impedance state.
IH
DC Characteristics
AC Characteristics
, but not within V
for RESET# parameters and to
IO
for the standby current specification.
S29GL-M MirrorBit
± 0.3 V, the device is in the standby mode, but the standby current is
IH
DC Characteristics
, output from the device is disabled. The output pins are placed in
D a t a
CC5
). If RESET# is held at V
TM
Flash Family
for the automatic sleep mode current
S h e e t
CE
RP
ACC
) for read access when the device is in ei-
Figure 15
, the device immediately terminates any
+ 30 ns. The automatic sleep mode is
IH
for the timing diagram.
IL
.) If CE# and RESET# are held
but not within V
S29GL-M_00_B8 February 7, 2007
SS
SS
±0.3 V, the
±0.3 V, the
IO