DA82562EM Intel, DA82562EM Datasheet - Page 125

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

7.2.1
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Note: The default values listed for the 82555 registers also apply to the registers in the embedded PHY
The individual registers are defined in the following subsections using the following conventions:
modules of the 82558 and 82559.
Control Register: Register 0
Bit
15
14
13
12
11
10
9
8
7
6:0
R: Read
W: Write
RO: Read only
SC: Self clearing
Name
Reset
Loopback
10/100
Auto-Negotiation Enable
Power Down
Isolate
Restart auto configuration
Full/Half
Collision Test Enable
Reserved
R / W
R/W
SC
R/W
R/W
R/W
R/W
R/W
R/W
SC
R/W
R/W
R/W
Description
1 = PHY reset
0 = normal operation
1 = loopback mode
0 = normal operation
1 = 100 Mbps
0 = 10 Mbps
1 = Enable Auto-Negotiation
0 = Disable Auto-Negotiation
1 = power down
0 = normal operation
1 = electrically isolate PHY from MII
0 = normal operation
1= Restart the auto negotiation
0 = Normal operation
1= Full duplex
0 = Half duplex
1 = enable the collision CDT test during loopback
Written as 0, don't care on read
Physical Layer Interface
Default
0
0
1
1
0
0
0
1
0
0
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