DA82562EM Intel, DA82562EM Datasheet - Page 73

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 40. 82557 Dual-Port FIFO Settings
Note: If a runtime algorithm for Adaptive IFS is implemented, it is recommended that software issue an 8
byte configure command. If any of the first 8 bytes needs to be re-configured and the last 14 bytes
do not need to be changed, then it is more appropriate to use an 8 byte configure command. This is
a more efficient way of re-configuring the device.
•
Binary (Transmit Bits 6:4 & Receive Bits 3:0)
Bits 5:0 - Byte Count. The byte count indicates the number of Command Block bytes to be
configured (and is always included in the count). It allows changing some of the parameters by
specifying a byte count less than the maximum number of configuration bytes (22 bytes). The
first eight bytes are used by the CU, and the remaining bytes are passed to the CSMA/CD unit
through the transmit DMA. The value permitted is 8 bytes.
Default - none.
Recommended -16h.
BYTE 1.
— Bits 6:4 - Transmit FIFO Limit. The transmit FIFO limit specifies the number of bytes
— Bits 3:0 - Receive FIFO Limit. The receive FIFO limit specifies the number of bytes
0
0
0
0
0
0
0
0
1
1
1
1
Configuration Value (Nibble Wide)
located in the 64 byte dual-ported transmit FIFO at which the device requests the bus in
order to transfer data from system memory to its internal transmit FIFO. The transmit
FIFO is organized in 32-bit wide Dwords. The FIFO limit programming is showed in the
table below.
Default - 0.
Recommended - 0.
located in the dual-ported receive FIFO at which the device requests the bus in order to
transfer data from its internal receive FIFO to system memory. The dual-ported receive
FIFO is organized into 32-bit wide Dwords. For the 82557, the FIFO size is 64 bytes. For
the 82558 and 82559 the FIFO is 128 bytes. The FIFO limit programming is showed in
the table below.
Default - 8.
Recommended - The default value is fine. However, lower values will result in better PCI
efficiency, whereas higher values will result in lower latencies.
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Dwords
Transmit FIFO Limit
0
1
2
3
4
5
6
7
0
1
2
3
Bytes
12
16
20
24
28
12
0
4
8
0
4
8
Host Software Interface
Dwords
Receive FIFO Limit
16
15
14
13
12
11
10
9
8
7
6
5
Bytes
32
64
60
56
52
48
44
40
36
28
24
20
a
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