DA82562EM Intel, DA82562EM Datasheet - Page 5

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

8
Appendices
A
B
Figures
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
1
2
3
4
5
6
7
8
9
10 SCB Command Word ................................................................................................................. 36
11 Self-Test Results Format ............................................................................................................ 43
12 EEPROM Control Register ......................................................................................................... 45
13 EEPROM Read Timing Diagram ................................................................................................ 48
14 General Action Command Format .............................................................................................. 58
15 NOP Command Format .............................................................................................................. 59
16 Individual Address Setup Command Format ..............................................................................60
17 Configure Command Format ...................................................................................................... 61
18 Multicast Setup Command Format ............................................................................................. 80
19 Transmit Command Format........................................................................................................81
7.4
7.5
Programming Recommendations ............................................................................................ 133
8.1
8.2
8.3
8.4
Wake-up Functionality .............................................................................................................. 137
82550 and 82551 Specific Information..................................................................................... 153
82557 Network Interface Card Block Diagram ............................................................................. 5
Command Register..................................................................................................................... 12
Command Register..................................................................................................................... 13
Cache Line Size.......................................................................................................................... 14
Base Address Register for Memory Mapping ............................................................................. 15
Base Address Register for I/O Mapping .....................................................................................15
Expansion ROM Base Address Register.................................................................................... 17
8255x Memory Architecture ........................................................................................................28
SCB Status Word........................................................................................................................ 34
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 10BASE-T Transmit Jabber Detect Counter: Register 25 ................................... 125
7.3.11 Equalizer Control and Status Register: Register 26 ............................................ 126
7.3.12 Special Control Register: Register 27.................................................................. 127
Auto-Negotiation Functionality ..........................................................................................128
7.4.1
7.4.2
Vendor-Specific PHY Programming ................................................................................. 130
7.5.1
7.5.2
Adapter Initialization ......................................................................................................... 133
8.1.1
8.1.2
8.1.3
Transmit Processing ......................................................................................................... 134
Frame Reception .............................................................................................................. 134
Interrupt Processing.......................................................................................................... 135
100BASE-TX Receive Error Frame Counter: Register 21 ................................... 125
Receive Symbol Error Counter: Register 22........................................................ 125
100BASE-TX Receive EOF Error Counter: Register 23 ......................................125
10BASE-T Receive EOF Error Counter: Register 24 .......................................... 125
Description ........................................................................................................... 128
Parallel Detection................................................................................................. 129
Intel 82555 TX PHY ............................................................................................. 130
82558 and 82559 Embedded PHY Unit............................................................... 130
8255x Initialization ...............................................................................................133
PHY Detection and Initialization .......................................................................... 133
NOS Specific Initialization.................................................................................... 134
Contents
v