DA82562EM Intel, DA82562EM Datasheet - Page 53

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

6.3.4
6.3.4.1
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 20. EEPROM Control Register Locations
Figure 12. EEPROM Control Register
Table 21. EEPROM Control Register Bits Definitions
EEPROM Control Register
The EEPROM control register is a 32-bit entity at offset 0Ch of the CSR space. They are used to
read from and enable writes to an external EEPROM component.
The serial EEPROM or equivalent integrated circuit (IC) stores configuration data for the
controller and the adapter. The EEPROM is a serial in and serial out device. Serial EEPROMs
range in size from 16 to 256 registers of 16 bits per register. All accesses, read or write, are
preceded by a command instruction to the device. The command instructions begin with a logical 1
as the start bit, two opcode bits (indicating read, write, erase, etc.), and n-bits of address. The
address field varies with the size of the EEPROM and is 6 bits for a 64 register EEPROM and 8 bits
for a 256 register device. The end of the address field is indicated by a dummy 0 bit from the
EEPROM, which indicates the entire address field has been transferred to the device. A command
is issued by asserting the chip select signal and clocking the data into the EEPROM on its data
input pin relative to the serial clock input. The chip select signal is de-asserted after the completion
of the EEPROM cycle (command, address and data).
CPU Accesses to the EEPROM
The EEPROM access port is shown below. This register is located at offset 0Eh in the device
Control register block. The CPU directly manipulates these bits to read to or write from the
EEPROM. There should be no other local bus activity at this time.
23:20
19
3. Writes a status word composed of the Complete OK bits (equals A000h at Dword 0). Prior to
Bit
23
X
the Dump Wake up packet command, the driver should initialize the status word to 0. After the
Dump Wake-up packet command, it should poll the status word for a completion status.
EEPROM Control Register
Upper Word (D31:D16)
EEDO
SCB Command Word
Symbol
22
X
Reserved.
Serial Data Out. This bit contains the value read from the EEPROM when
performing a read operation on the EEPROM.
21
X
SCB General Pointer
20
X
PORT
EEDO
19
Lower Word (D15:D0)
SCB Status Word
Description
Reserved
EEDI
18
EECS
17
Host Software Interface
EESK
16
Base + Ch
Base + 0h
Base + 4h
Base + 8h
Offset
45