TE28F128J3C150 Intel, TE28F128J3C150 Datasheet - Page 29
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TE28F128J3C150
Manufacturer Part Number
TE28F128J3C150
Description
Manufacturer
Intel
Datasheet
1.TE28F128J3C150.pdf
(72 pages)
Specifications of TE28F128J3C150
Cell Type
NOR
Density
128Mb
Access Time (max)
150ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
24/23Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
16M/8M
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TE28F128J3C150
Manufacturer:
INTEL
Quantity:
20 000
7.4
7.5
Datasheet
Figure 14. AC Waveform for Reset Operation
Table 11. Reset Specifications
Figure 15. Transient Input/Output Reference Waveform for V
Reset Operation
NOTE: STS is shown in its default mode (RY/BY#).
AC Test Conditions
NOTE: AC test inputs are driven at V
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not
3. A reset time, t
P1
P2
#
executing then the minimum required RP# Pulse Low Time is 100 ns.
outputs are valid.
STS (R)
RP# (P)
t
t
output timing ends, at V
PLPH
PHRH
V
Sym
CCQ
0.0
Input V
V
V
V
V
PHQV
IH
IH
RP# Pulse Low Time
(If RP# is tied to V
applicable)
RP# High to Reset during Block Erase, Program, or
Lock-Bit Configuration
IL
IL
, is required from the latter of STS (in RY/BY# mode) or RP# going high until
CCQ
/2
CCQ
P1
/2 V (50% of V
CC
CCQ
, this specification is not
Parameter
for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and
CCQ
Test Points
P2
). Input rise and fall times (10% to 90%) < 5 ns.
CCQ
= 2.7 V–3.6 V
Min
35
V
256-Mbit J3 (x8/x16)
Max
100
CCQ
/2
Unit
Output
µs
ns
Notes
1,2
1,3
29