TE28F128J3C150 Intel, TE28F128J3C150 Datasheet - Page 9
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TE28F128J3C150
Manufacturer Part Number
TE28F128J3C150
Description
Manufacturer
Intel
Datasheet
1.TE28F128J3C150.pdf
(72 pages)
Specifications of TE28F128J3C150
Cell Type
NOR
Density
128Mb
Access Time (max)
150ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
24/23Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
16M/8M
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TE28F128J3C150
Manufacturer:
INTEL
Quantity:
20 000
2.1
Datasheet
A[MAX:MIN]
Figure 1. 3 Volt Intel StrataFlash
VCCQ
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS signal to be configured to
pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design (see
Table 13, “Chip Enable Truth Table” on page
multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-
chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit
mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit
operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A
device block diagram is shown in Figure 4 on page 14.
When the device is disabled (see
standby mode is enabled. When RP# is at V
minimizes power consumption and provides write protection during reset. A reset time (t
required from RP# going high until data outputs are valid. Likewise, the device has a wake time
(t
and the Status Register is cleared.
Block Diagram
Input Buffer
Address
Address
Counter
PHWL
Latch
) from RP#-high until writes to the CUI are recognized. With RP# at V
A[2:0]
Y-Decoder
X-Decoder
®
Memory Block Diagram
Output
Buffer
Table 13 on page
128-Mbit: One-hundred
Comparator
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Kbyte Blocks
Identifier
Register
Register
Status
Query
D[15:0]
Data
twenty-eight
Y-Gating
IL
33) reduces decoder logic typically required for
, a further power-down mode is enabled which
Input Buffer
33), with CEx at V
Multiplexer
Write State
Machine
Command
Interface
User
IH
and RP# at V
256-Mbit J3 (x8/x16)
IL
Program/Erase
Voltage Switch
, the WSM is reset
I/O Logic
Logic
IH
CE
, the
PHQV
STS
WE#
OE#
RP#
VCC
VPEN
CE0
CE1
CE2
GND
BYTE#
VCC
) is
9