TE28F128J3C150 Intel, TE28F128J3C150 Datasheet - Page 6
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TE28F128J3C150
Manufacturer Part Number
TE28F128J3C150
Description
Manufacturer
Intel
Datasheet
1.TE28F128J3C150.pdf
(72 pages)
Specifications of TE28F128J3C150
Cell Type
NOR
Density
128Mb
Access Time (max)
150ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
24/23Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
16M/8M
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TE28F128J3C150
Manufacturer:
INTEL
Quantity:
20 000
Contents
6
Revision
07/27/01
10/31/01
03/21/02
12/12/02
01/24/03
12/09/03
11/23/04
Date of
1/23/04
1/23/04
5/19/04
3/24/05
1/3/04
7/7/04
Version
-009
-010
-012
-013
-014
-015
-016
-016
-018
-019
-020
-021
-011
Added Figure 4, 3 Volt Intel StrataFlash
Added Figure 5, 3 Volt Intel StrataFlash
Specifications
Updated Operating Temperature Range to Extended (Section 6.1 and Table 22)
Reduced t
Added parameter values for –40 °C operation to Lock-Bit and Suspend Latency
Updated V
Removed Note #4, Section 6.4 and Section 6.6
Minor text edits
Added notes under lead descriptions for VF BGA Package
Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics
Removed byte mode read current row un DC characteristics
Added ordering information for VF BGA Package
Minor text edits
Changed datasheet to reflect the best known methods
Updated max value for Clear Block Lock-Bits time
Minor text edits
Added nomenclature for J3C (0.18 µm) devices.
Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128
Mb J3C device. Added “TE” package designator for J3C TSOP package.
Revised Asynchronous Page Read description. Revised Write-to-Buffer flow
chart. Updated timing waveforms. Added 256-Mbit J3C pinout.
Added 256Mbit device timings, device ID, and CFI information. Also corrected
VLKO specification.
Corrected memory block count from 257 to 255.
Memory block count fix.
Restructured the datasheet layout.
Added lead-free part numbers and 8-word page information.
Added Note to DC Voltage Characteristics table; “Speed Bin” to Read Operations
table; Corrected format for AC Waveform for Reset Operation figure; Corrected
“R” and “8W” headings in Enhanced Configuration Register table because they
were transposed; Added 802 and 803 to ordering information and corrected 56-
Lead TSOP combination number.
Corrected ordering information.
EHQZ
LKO
and V
to 35 ns. Reduced t
PENLK
to 2.2 V
Description
WHEH
®
®
Memory VF BGA Package (32 Mbit)
Memory VF BGA Mechanical
to 0 ns
Datasheet