TE28F128J3C150 Intel, TE28F128J3C150 Datasheet - Page 33
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TE28F128J3C150
Manufacturer Part Number
TE28F128J3C150
Description
Manufacturer
Intel
Datasheet
1.TE28F128J3C150.pdf
(72 pages)
Specifications of TE28F128J3C150
Cell Type
NOR
Density
128Mb
Access Time (max)
150ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
24/23Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
16M/8M
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TE28F128J3C150
Manufacturer:
INTEL
Quantity:
20 000
9.1.1
9.1.2
9.1.3
Datasheet
Table 13. Chip Enable Truth Table
Bus Read Operation
To perform a bus read operation, CEx (refer to
CEx is the device-select control; when active, it enables the flash memory device. OE# is the data-
output control; when active, the addressed flash memory data is driven onto the I/O bus. For all
read states, WE# and RP# must be de-asserted. See
Refer to
and refer to
states.
Bus Write Operation
Writing commands to the Command User Interface enables various modes of operation, including
the reading of array data, CFI data, identifier codes, inspection and clearing of the Status Register,
and, when V
The Block Erase command requires appropriate command data and an address within the block to
be erased. The Byte/Word Program command requires the command and address of the location to
be written. Set Block Lock-Bit commands require the command and block within the device to be
locked. The Clear Block Lock-Bits command requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see
page
Output Disable
With CEx asserted, and OE# at a logic-high level (V
signals D[15:0] are placed in a high-impedance state.
NOTE: For single-chip applications, CE2 and CE1 can be connected to V
33). Standard microprocessor write timings are used.
CE2
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
IL
Section 10.0, “Read Operations” on page 37
Section 14.0, “Special Modes” on page 50
PEN
= V
PENH
CE1
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
IL
, block erasure, program, and lock-bit configuration.
CE0
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
IL
Table 13 on page
Section 7.1, “Read Operations” on page
IH
for details on reading from the flash array,
), the device outputs are disabled. Output
for details regarding all other available read
Disabled
Disabled
Disabled
Disabled
DEVICE
Enabled
Enabled
Enabled
Enabled
33) and OE# must be asserted.
IL
.
256-Mbit J3 (x8/x16)
Table 13 on
22.
33