TE28F400B3B90 Intel, TE28F400B3B90 Datasheet - Page 18

• Manufacturer Part Number: TE28F400B3B90
• Manufacturer: Intel

Specifications of TE28F400B3B90

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 18b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 256K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.1.5
3.2
3.2.1
12
If RP# is taken low for time t
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence:
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or Block-Erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the
flash memory may be providing status information instead of array data. Intel
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
Write
A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard microprocessor write timings to control Flash
operations. The CUI does not occupy an addressable memory location. The address and data buses
are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first.
illustrates a Program and Erase operation.
provides detailed information on moving between the different modes of operation using CUI
commands.
Two commands modify array data: Program (40H), and Erase (20H). Writing either of these
commands to the internal Command User Interface (CUI) initiates a sequence of internally timed
functions that culminate in the completion of the requested task (unless that operation is aborted by
either RP# being driven to V
Modes of Operation
The flash memory has four read modes (read array, read identifier, read status, and read query; see
Appendix
suspend to program, erase suspend to read, and program suspend to read) are available only during
suspended operations.
is a comprehensive chart showing the state transitions.
Read Array
When RP# transitions from V
respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
1. When RP# goes low, the device shuts down the operation in progress, a process that takes time
2. After this time t
3. In both cases, after returning from an aborted operation, the relevant time t
t
t
t
paragraph. However, in this case, these delays are referenced to the end of t
when RP# goes high.
PLRH
PLRH
PHEL
,
B), and two write modes (program and block erase). Three additional modes (erase
must be waited before a Read or Write operation is initiated, as discussed in the previous
to complete.
Figure
10B), or enter reset mode (if RP# is still logic low after t
PLRH
Table 4
, the part will either reset to read-array mode (if RP# has gone high during
IL
PLPH
IL
summarizes the commands used to reach these modes.
for t
(reset) to V
during a Program or Erase operation, the operation will be
PLRH
or an appropriate Suspend command).
Table 6
IH
, the device defaults to read-array mode and will
shows the available commands, and
PLRH
®
PHQV
Flash memories
PLRH
,
Figure
or t
rather than
Appendix A
Appendix A
Figure 9
Preliminary
PHWL
10C).
/