LPC2214FBD144 NXP Semiconductors, LPC2214FBD144 Datasheet - Page 16

• Manufacturer Part Number: LPC2214FBD144
• Manufacturer: NXP Semiconductors

Specifications of LPC2214FBD144

• Cpu Family: LPC2000
• Device Core: ARM7TDMI-S
• Device Core Size: 16/32Bit
• Frequency (max): 60MHz
• Interface Type: I2C/SPI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 16KB
• # I/os (max): 112
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/2.5/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
LPC2212_2214_4
Product data sheet
6.8.1 Features
6.8.2 Features added with the Fast GPIO set of registers available on
6.6 Pin connect block
6.7 External memory controller
6.8 General purpose parallel I/O (GPIO) and Fast I/O
[1]
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
The external Static Memory Controller (SMC) is a module which provides an interface
between the system bus and external (off-chip) memory devices. It provides support for
up to four independently configurable memory banks (16 MB each with byte lane enable
control) simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash
EPROM, burst ROM memory, or some external I/O devices.
Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
Device pins that are not connected to a specific peripheral function are controlled by the
parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
LPC2212/2214/01 only
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SSP interface available on LPC2212/01 and LPC2214/01 only.
Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
Direction control of individual bits.
Separate control of output set and clear.
All I/O default to inputs after reset.
Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O
timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
All Fast GPIO registers are byte addressable.
Entire port value can be written in one instruction.
Ports are accessible via either the legacy group of registers (GPIOs) or the group of
registers providing accelerated port access (Fast GPIOs).
Rev. 04 — 3 January 2008
16/32-bit ARM microcontrollers
LPC2212/2214
© NXP B.V. 2008. All rights reserved.
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