ISP1761BE STEricsson, ISP1761BE Datasheet - Page 139
![no-image](/images/manufacturer_photos/0/6/636/stericsson_sml.jpg)
ISP1761BE
Manufacturer Part Number
ISP1761BE
Description
Manufacturer
STEricsson
Datasheet
1.ISP1761BE.pdf
(164 pages)
Specifications of ISP1761BE
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1761BE
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
ISP1761_5
Product data sheet
15.1.2.1 Single cycle: DMA read
15.1.2 DMA timing
Table 170. Memory read
T
In the following sections:
Table 171. DMA read (single cycle)
T
Symbol
t
t
t
Symbol
V
t
t
t
t
t
t
t
V
t
t
t
t
w13
su13
su23
a14
a24
d14
w14
a34
a44
h14
a14
a24
d14
w14
amb
amb
Fig 24. DMA read (single cycle)
•
•
CC(I/O)
CC(I/O)
Polarity of DACK is active HIGH
Polarity of DREQ is active HIGH
= 40 C to +85 C; unless otherwise specified.
= 40 C to +85 C; unless otherwise specified.
= 1.65 V to 1.95 V
= 3.3 V to 3.6 V
Parameter
RD_N pulse width
CS_N set-up time before RD_N LOW
address set-up time before RD_N LOW
Parameter
DACK assertion time after DREQ assertion
RD_N assertion time after DACK assertion
data valid time after RD_N assertion
RD_N pulse width
DREQ de-assertion time after RD_N assertion
DACK de-assertion to next DREQ assertion time -
data hold time after RD_N de-asserts
DACK assertion time after DREQ assertion
RD_N assertion time after DACK assertion
data valid time after RD_N assertion
RD_N pulse width
DREQ
DACK
RD_N
DATA
Rev. 05 — 13 March 2008
…continued
t
a14
t
a24
t
d14
t
w14
t
a34
t
h14
t
a44
Min
21
0
0
Min
0
0
-
> t
-
-
0
0
-
> t
Hi-Speed USB OTG controller
d14
d14
Max
-
-
-
Max
-
-
24
-
29
56
5
-
-
20
-
004aaa530
© NXP B.V. 2008. All rights reserved.
ISP1761
Unit
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
138 of 163