ISP1761BE STEricsson, ISP1761BE Datasheet - Page 162
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ISP1761BE
Manufacturer Part Number
ISP1761BE
Description
Manufacturer
STEricsson
Datasheet
1.ISP1761BE.pdf
(164 pages)
Specifications of ISP1761BE
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1761BE
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
26. Contents
1
2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.1.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
7.6
7.7
7.7.1
7.8
7.9
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
ISP1761_5
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 14
Host controller . . . . . . . . . . . . . . . . . . . . . . . . . 32
Host/peripheral roles. . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
ISP1761 internal architecture: advanced
NXP slave host controller and hub . . . . . . . . . 14
Internal clock scheme and port selection . . . . 15
Host controller buffer memory block . . . . . . . . 16
General considerations. . . . . . . . . . . . . . . . . . 16
Structure of the ISP1761 host controller
memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Accessing the ISP1761 host controller
memory: PIO and DMA . . . . . . . . . . . . . . . . . 19
PIO mode access, memory read cycle . . . . . . 20
PIO mode access, memory write cycle . . . . . 20
PIO mode access, register read cycle . . . . . . 21
PIO mode access, register write cycle . . . . . . 21
DMA mode, read and write operations . . . . . . 21
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Phase-Locked Loop (PLL) clock multiplier . . . 24
Power management . . . . . . . . . . . . . . . . . . . . 25
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 26
Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Overcurrent detection . . . . . . . . . . . . . . . . . . . 29
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 30
EHCI capability registers . . . . . . . . . . . . . . . . 33
CAPLENGTH register. . . . . . . . . . . . . . . . . . . 33
HCIVERSION register . . . . . . . . . . . . . . . . . . 33
HCSPARAMS register . . . . . . . . . . . . . . . . . . 33
HCCPARAMS register . . . . . . . . . . . . . . . . . . 34
EHCI operational registers . . . . . . . . . . . . . . . 35
USBCMD register . . . . . . . . . . . . . . . . . . . . . . 35
USBSTS register . . . . . . . . . . . . . . . . . . . . . . 36
USBINTR register . . . . . . . . . . . . . . . . . . . . . . 37
FRINDEX register . . . . . . . . . . . . . . . . . . . . . . 37
CONFIGFLAG register . . . . . . . . . . . . . . . . . . 38
PORTSC1 register . . . . . . . . . . . . . . . . . . . . . 39
ISO PTD Done Map register. . . . . . . . . . . . . . 40
ISO PTD Skip Map register . . . . . . . . . . . . . . 41
Rev. 05 — 13 March 2008
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
9
9.1
9.2
9.3
9.3.1
9.3.2
9.4
9.4.1
9.4.2
9.4.3
9.5
9.5.1
9.5.1.1
OTG controller . . . . . . . . . . . . . . . . . . . . . . . . 85
ISO PTD Last PTD register . . . . . . . . . . . . . . 41
INT PTD Done Map register. . . . . . . . . . . . . . 41
INT PTD Skip Map register . . . . . . . . . . . . . . 41
INT PTD Last PTD register . . . . . . . . . . . . . . 42
ATL PTD Done Map register . . . . . . . . . . . . . 42
ATL PTD Skip Map register . . . . . . . . . . . . . . 42
ATL PTD Last PTD register . . . . . . . . . . . . . . 43
Configuration registers . . . . . . . . . . . . . . . . . . 43
HW Mode Control register . . . . . . . . . . . . . . . 43
HcChipID register. . . . . . . . . . . . . . . . . . . . . . 45
HcScratch register . . . . . . . . . . . . . . . . . . . . . 45
SW Reset register . . . . . . . . . . . . . . . . . . . . . 45
HcDMAConfiguration register. . . . . . . . . . . . . 46
HcBufferStatus register . . . . . . . . . . . . . . . . . 47
ATL Done Timeout register . . . . . . . . . . . . . . 48
Memory register . . . . . . . . . . . . . . . . . . . . . . . 48
Edge Interrupt Count register. . . . . . . . . . . . . 49
DMA Start Address register . . . . . . . . . . . . . . 50
Power Down Control register . . . . . . . . . . . . . 51
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . 53
HcInterrupt register . . . . . . . . . . . . . . . . . . . . 53
HcInterruptEnable register . . . . . . . . . . . . . . . 55
ISO IRQ MASK OR register . . . . . . . . . . . . . . 57
INT IRQ MASK OR register . . . . . . . . . . . . . . 57
ATL IRQ MASK OR register . . . . . . . . . . . . . . 57
ISO IRQ MASK AND register. . . . . . . . . . . . . 58
INT IRQ MASK AND register . . . . . . . . . . . . . 58
ATL IRQ MASK AND register . . . . . . . . . . . . . 58
Philips Transfer Descriptor (PTD). . . . . . . . . . 58
High-speed bulk IN and OUT . . . . . . . . . . . . . 61
High-speed isochronous IN and OUT . . . . . . 65
High-speed interrupt IN and OUT . . . . . . . . . 69
Start and complete split for bulk . . . . . . . . . . . 73
Start and complete split for isochronous . . . . 77
Start and complete split for interrupt . . . . . . . 81
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Dual-role device . . . . . . . . . . . . . . . . . . . . . . . 85
Session Request Protocol (SRP) . . . . . . . . . . 86
B-device initiating SRP. . . . . . . . . . . . . . . . . . 86
A-device responding to SRP . . . . . . . . . . . . . 86
Host Negotiation Protocol (HNP) . . . . . . . . . . 87
Sequence of HNP events . . . . . . . . . . . . . . . . 87
OTG state diagrams . . . . . . . . . . . . . . . . . . . . 88
HNP implementation and OTG state machine 90
OTG controller registers . . . . . . . . . . . . . . . . . 91
Device Identification registers . . . . . . . . . . . . 92
Vendor ID register . . . . . . . . . . . . . . . . . . . . . 92
Hi-Speed USB OTG controller
© NXP B.V. 2008. All rights reserved.
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