AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet
AT86RF211SAHW
Specifications of AT86RF211SAHW
Related parts for AT86RF211SAHW
AT86RF211SAHW Summary of contents
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Datasheet 1. Features • Up-compatibility with the AT86RF211 – Same Features as AT86RF211 after Power-on Reset – New Features Activated by a Bit (ADDFEAT) • Shrink Version with a Current Consumption Reduction of 20% • Direct Replacement in Production • ...
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Description The AT86RF211S is a shrink version of the AT86RF211. In addition to cost reduction, the use of the lat- est RF e2v process provides a high level of robustness and performance (high output power) and significantly improves some ...
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Faster RSSI The ADC clock period can now be decreased from 12 µs to 1.5 µs. Faster channel scanning in multi- channel applications or LBT (Listen Before Transmit) is then possible, as well as ASK demodulation for low data ...
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Figure 3-1. Asynchronous Transparent Transmit Mode Companion Microcontroller 3.4 Asynchronous Transparent Receive Mode Set up by the MCU in receive mode, the AT86RF211S demodulates any data available on the antenna. The data is given on the DATAMSG pin in real-time ...
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Synchronous Receive Modes In addition to the modes described above, the AT86RF211S provides a clock signal that facilitates recovery of data by any low-cost MCU (no UART controller, for instance). The data can also be synchronized on this clock ...
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Figure 3-4. Wake-up Overview Step 2: The chip wakes up periodically, waiting for an expected message (stand-alone operation) Step 1: The chip is set-up in sleep mode using the 3-wire interface (SLE, SCK, SDATA), then the microcontroller goes to sleep, ...
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Selecting the Operating Mode Figure 3-6. Flowchart e2v semiconductors SAS 2008 AT86RF211S 7 0894C–WIRE–11/08 ...
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Block Diagram Figure 3-7. AT86RF211S Block Diagram RF FILTER These are the only blocks that depend on the selected ISM band (433, 868 or 915 MHz): dual band applications can be done by only switching them. Synthesizer, loop filter, ...
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Pin Description Table 3-2. Pinout Pin Name Comments 1 RPOWER Full-scale output power resistor 2 TXGND1 GND input/output 4 TXGND2 GND 5 TXGND3 GND 6 TXGND4 GND 7 TXVCC VCC 8 TXGND5 GND 9 DIGND GND ...
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Detailed Description 4.1 Frequency Synthesis 4.1.1 Crystal Reference Oscillator The reference clock is based on a classic Colpitts architecture with three external capacitors. The bias circuitry of the oscillator is optimized to produce a low drive level for the ...
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Table 4-1. XTO Frequencies Reference Clock Frequency IF1 Frequency 10.245 MHz 10.7 MHz It is preferable to add a resistor (3.3 kΩ) between XTAL2 and GND. This decreases the settling time of the XTO to typically 8 ms with an ...
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Synthesizer A high-speed, high-resolution multi-loop synthesizer is integrated. The synthesizer can operate within two frequency bands: 400 to 480 MHz and 800 to 950 MHz. All channels within these two bands can be selected by programming registers F0 to ...
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Receiver Description 4.2.1 Intermediate Frequencies For selectivity and flexibility purposes, a classic and robust 2 IF super-heterodyne architecture has been selected for the AT86RF211S. To minimize the cost of the external components, the most popular IF val- ues has ...
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First LNA/Mixer The LNA mixer exhibits a gain of approximately the reduced gain is selected) over a 1.2 GHz bandwidth. Its noise figure is typically 900 MHz (10 dB with a ...
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The first mixer translates the input RF signal down to 10.7 MHz. The local oscillator is provided by the same synthesizer that generates a local frequency 10.7 MHz away from the Tx carrier frequency. The output impedance of the mixer ...
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Figure 4-11. Schematic Output of the Second Mixer 4.2.7 IF1 Narrow Bandwidth Filters IF1 and IF2 filters can be replaced by a single narrowband 10.7 MHz crystal filter. This solution has the following advantages: • Only one cheap IF1 filter ...
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The 10 nF capacitors cut the DC response. The first network has the low cut-off frequency and the sec- ond network the high cut-off frequency. 4.2.9 IF2 Amplifier Chain The input impedance of the IF2 amplifier is 1700Ω. This value ...
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RSSI Output The RSSI value can be read as a 6-bit word in the Status register. Its value is given in dB and is linear as shown in Figure 4-14 on page Figure 4-14. Typical RSSI Output (Board Implementation, ...
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Figure 4-15. ADC Converter Input Selection Vcc Supply DISCOUT (MOFFSET) Note: For voltage measurement, the LSB weighs 85 mV and the reference voltage is 1.25V. In Reception mode, please remember that both RSSI and V The clocking period on the ...
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FSK Demodulator The structure of the FSK demodulator is based on an oscillator. Figure 4-16. FSK Demodulator Schematic Fin The oscillator’s natural frequency is F oscillator’s output (point A in The XOR function translates the difference into a pulse ...
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Given below are examples of possible configurations in the 600 kHz-wide 868 to 868.6 MHz European sub-band, in which the European standard EN 300 220 is applicable: • SDB: 4 channels at 19.200 bps • MDB: 2 channels at 5.000 ...
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Internal Mode The internal mode uses the output of a DAC as the comparison level. Once this threshold has been cor- rectly set, an absolute data slicing of the demodulated signal is possible; there is no need for a ...
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These procedures are made automatically by the software. Refer to the Application Note “Data Demodu- lation and Crystal Selection with the AT86RF211S” reference 5418. 4.2.12.3 Charge and Hold Mode After a single charge phase (for example, during a preamble), the ...
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Power Amplification The Power Amplifier has been built to deliver more than 14 dBm ( the three most common fre- quency bands). This power level is intended to be measured on the aerial port with a correct ...
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Figure 4-23. ALC of the Power Amplifier Figure 4-24. Typical Output Power of the PA for T = 25°C and V 4.3.2 Hardware Control R sets the maximum power delivered by the internal Power Amplifier by limiting the current it ...
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Figure 4-25. R POWER Note: Keeping the PA output matched guarantees maximum power efficiency. 4.3.3 Software Control The power can then be adjusted from the value set below this value, by programming bits ...
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Digital Features 4.4.1 Clock Recovery Function 4.4.1.1 Preamble The clock recovery algorithm in the AT86RF211S has been improved and the new algorithm must be used. To use the new algorithm: 1. Put the device into RF211S mode: ADDFEAT = ...
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DATA transition; the clock is moved later or sooner, depending on the gap between CLOCK and DATA. For example: If DATARATE = 50 kbps, which is equivalent to a duration of 200 × T for 1 ...
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Data Tolerance Programming Table 4-9 provides some examples of tolerance values with tolerance = 4% × DATARATE. Table 4-9. Tolerance Values with Tolerance Equal to 4% × Data Rate DATATOL[7:0] (4) 10 (8) 10 (vv) 10 (41) 10 (43) ...
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Figure 4-27. Clock Recovery Target Position First random position of clock's rising edge Note: Use the above settings to ensure a good trade-off between the settling time and the jitter of the clock. The clock remains correct, regardless of the ...
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PLL Lock Detect The PLL lock function uses up and down signals from the internal phase detector. These signals are analyzed synchronously with a clock frequency, depending on the LDCK bit programming: • N0LD2 triggers the PLL’s unlock condition ...
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Table 4-12. Wake-up Period Programming (Continued) WPER[8:0] WPER[8:7] (17f) or (0ff) (10) or (01 (181) (11 (182) (11 – (11) 2 (1fe) (11 (1ff) (11 4.5.2 WL1 Programming WL1 ...
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WL2 programming WL2 can be set as a multiple of WL1 from WL1. Table 4-14. WL2 Programming WL2[2:0] (000) 2 (001) 2 (010) 2 (011) 2 (100) 2 (101) 2 (110) 2 (111) 2 More information ...
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WRITE Mode (R The address, R/W and data bits are clocked on the rising edge of SCK. If the number of data bits is lower than the register capacity, the LSB bits retain their former value, allow- ...
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READ Mode (R The address and R/W bits are clocked on the rising edge of SCK and the data bits are changed on the falling edge of SCK. The register’s MSB is the first bit read. The ...
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Figure 4-33. Chronogram with Timing tdle SLE T SCK SDATA A[3] A[2 ] SDATA INPUT Direction Note: For timing specifications, refer to 4.6.2 Registers Table 4-15. Register Overview Name Address A[3:0] F0 (0000 (0001 (0010) 2 ...
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Reset Register (RESET) Writing in this register ( triggers an asynchronous reset. This register can only be written. All registers return to the reset state. The chip returns to power-down mode. All the following blocks are reset: ...
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Table 4-17. CTRL1 Detailed Description Name Number of Bits Comments General power-down 0: power down mode; only the serial interface is active PDN 1 1: AT86RF211S activated Reset value: 0 Reception or transmission selection 0: Rx mode RXTX 1 1: ...
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Table 4-17. CTRL1 Detailed Description Name Number of Bits Comments – 1 reserved, must be kept to reset value frequency selection (00) RXFS 2 (01) Reset value: (10) Crystal frequency 0: 10.245 MHz (when IF1 = 10.7 MHz) ...
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Table 1. RSSI Working Example MRSSI Sequence 27 RSSI level NOK NOK DATAMSG 4.6.2.3 Control Register (CTRL2) Table 4-18. CTRL2 Overview Name DATARATE nbit 31-18 init (0000) 16 Register reset value = (00000057) 16 Table 4-19. CTRL2 Detailed Description Number ...
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Frequency Registers Table 4-20. Overview Name F0, F1, F2, F3 Table 4-21. Detailed Description Name Number of bits Note: 1. F0, F1, F2 and F3 registers must be programmed before using ...
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Table 4-23. Programmed Frequency Mode RX TX Example: FCHANNEL = 868.3 MHz IF1 = 10.7 MHz Deviation = ±4 kHz Table 4-24. Programmed Frequency Example Mode RX TX Notes reception mode, one of the two frequencies (879 or ...
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Table 4-26. Detailed Description Name PLLL MRSSI MVCC WAKEUP - MSGERR MSGDATL MSGMRATE e2v semiconductors SAS 2008 Number of Bits Comments PLL Lock flag 0: PLL unlocked 1 1: PLL locked Reset value: 0 Measured RSSI level 6 Reset value: ...
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DTR Register DTR contains the bits corresponding to the new features of the AT86RF211S. Depending on the CTRL1[0] value, DTR has two different sizes: • CTRL1[ DTR[5:0] - (same as AT86RF211) • CTRL1[ ...
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DTR Overview in RF211S Mode (Continued) Name PORTEN PORTPOL nbit 20 19 init 0 0 DTR Overview in RF211S Mode (Continued) Name WUSYNC WUHEAD nbit 10 init 0 Table 4-30. DTR Detailed Description in RF211S Mode Name Number of Bits ...
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Table 4-30. DTR Detailed Description in RF211S Mode (Continued) Name Number of Bits RSSICLK 2 – 1 PORTEN 1 PORTPOL 1 PORTSEL 3 CLKOUTPUT 2 NEWDATACLK 1 SYNCDATAMSG 1 DATACLKEN 1 WUSYNC 1 46 0894C–WIRE–11/08 Comments RSSI clock selection control ...
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Table 4-30. DTR Detailed Description in RF211S Mode (Continued) Name Number of Bits WUHEAD 1 – 3 DSREF 4 DISCHIGH 1 DISCLOW 1 Notes: 1. The hold time on the SKFILT capacitor depends on the value of this capacitor. This ...
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Table 4-32. WUC Detailed Description Name Number of Bits Comments Wake-up function enable Returns to “0” when a valid message is received. 0: wake-up disable WUE 1 1: wake-up enable Reset value: 0 Data content 0: message without data field ...
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Table 4-32. WUC Detailed Description (Continued) Name Number of Bits Comments Minimum delay between TEST 1 and TEST 2 (check of header detection) Variable as multiple of WL1 from × WL1 WL2 3 Reset value: 2 × ...
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Wake -up Address Register (WUA) Table 4-35. WUA Overview Name nbit init Table 4-36. WUA Detailed Description Name Number of Bits ADDL 5 ADD 20 In this register, the last bit of the address field is not taken into ...
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Electrical Specification This device is sensitive to electro-static discharge (ESD). Storage or handling of the device must be carried out according to usual protection rules. Table 5-1. Absolute Maximum Ratings Temperature Storage temperature Supply voltage Digital input voltage RXIN ...
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Figure 5-1. Voltage vs. Temperature T˚ ( -20 -40 2.4 Note: The utilization range of the product described in Table 5-3. Digital CMOS DC Characteristics (unless otherwise specified, data is given for T ...
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Table 5-4. Timings Name Parameter CMOS rise/fall times F SCK frequency T SCK period tw SCK low or high time tsd SDATA setup before SCK rising thd SDATA hold after SCK rising SDATA output propagation delay after ...
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Table 5-6. Receiver Specification (unless otherwise specified, data is given for T = 25°C and V Parameter Min FSK sensitivity Noise figure Input IP3 LO leakage Co-channel rejection Image frequency rejection LNA-mixer gain LNA-mixer noise figure 1dB compression point Optimum ...
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Table 5-6. Receiver Specification (unless otherwise specified, data is given for T = 25°C and V (Continued) Parameter Min 1 MHz blocking 433/868/915 MHz 2 MHz blocking 433/868/915 MHz 5 MHz blocking 433/868/915 MHz 10 MHz blocking 433/868/915 MHz ACR ...
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Figure 5-2. Detailed Current in Rx Mode 2.25 2.5 Figure 5-3. Typical Supply Current in Rx Mode 28.0 26.0 24.0 22.0 2.25 2.5 56 0894C–WIRE–11/08 2.75 3 3.25 Vcc (V) 2.75 3 3.25 Vcc ...
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Table 5-7. Transmitter Specification (unless otherwise specified, data is given for T = 25°C, V and kΩ) POWER Parameter Output power Output power Output power Harmonic 2 at 433 MHz Harmonic 3 at 433 MHz Harmonic ...
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Figure 5-4. Typical Expected Supply Current in Tx Mode Figure 5-5. Typical Expected Detailed Current in Tx Mode 434 MHz 58 0894C–WIRE–11/08 50.00 45.00 40.00 35.00 30.00 25.00 20.00 15.00 2.25 2.50 2.75 Vsupply (V) 25.00 20.00 ...
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Typical Application 6.1 Implementation Figure 6-1. Full Example Schematic Rpower ANTENNA Note: Accurate information regarding the parts and values of the components to be used with the AT86RF211S is described in ...
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Layout 6.2.1 Reference Design – Top Layer Each unused area must be filled with copper and connected to the bottom side ground plane Decoupling capacitors remain close to the supply pins 6.2.2 Reference Design – Bottom Layer One-block ground ...
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... Full Part Number Package AT68RF211SAHW TQFP48 AT86RF211SAHW-R TQFP48 The AT86RF211S can be delivered in die form. Please contact your local e2v sales office. Tape & reel may be delivered in one or two different reels tied up together and may also come from two different lots. e2v semiconductors SAS 2008 ...
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AT86RF211S e2v semiconductors SAS 2008 ...
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Table of Contents 1 Features .................................................................................................... 1 2 Description ............................................................................................... 2 3 General Overview .................................................................................... 2 3.1 List of New Features ............................................................................................. 2 3.2 Low-power Standby Modes .................................................................................. 3 3.3 Asynchronous Transparent Transmit Mode .......................................................... 3 3.4 Asynchronous Transparent Receive ...
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How to reach us Home page: www.e2v.com Sales offices: Europe Regional sales office e2v ltd 106 Waterhouse Lane Chelmsford Essex CM1 2QU England Tel: +44 (0)1245 493493 Fax:: +44 (0)1245 492492 mailto: enquiries@e2v.com Europe Regional sales office e2v sas 16 ...