AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet - Page 47

• Manufacturer Part Number: AT86RF211SAHW
• Manufacturer: Atmel

Specifications of AT86RF211SAHW

• Lead Free Status / Rohs Status: Compliant

Table 4-30.
Notes:
4.6.2.8
Table 4-31.
WUC Overview (Continued)
e2v semiconductors SAS 2008
Name
WUHEAD
–
DSREF
DISCHIGH
DISCLOW
Name
Name
nbit
nbit
init
init
1. The hold time on the SKFILT capacitor depends on the value of this capacitor. This is detailed in the Application Note
2. SDB and NDB are like the CTRL1[6] selection. Medium DB offers a slope
3. The reference clock used for the DIGOUT output clock is the crystal frequency, in relation with the chosen division ratio.
4. DSREF, DISCHIGH and DISCLOW are unchanged compared to the AT86RF211 selection.
5. If CTRL1[0] = '1' (ADDFEAT) and DTR is left to the default setting, then the AT86RF211S has the same features as the
“AT86RF211S FSK Transceiver for ISM Radio Applications - RF BOM versus Application Requirements”.
(mV / kHz) that is one third of the NDB one, and wide DB a slope of one fifth of the NDB one, allowing wider deviations.
AT86RF211. Exception: if CTRL1[6] is NDB, it is then set to SDB which is the default value of DTR[26-25] .
Wake-up Control Register
DTR Detailed Description in RF211S Mode (Continued)
WUC Overview
Register reset value = (7f8be110)
WUE
31
0
(010)
Number of Bits
WL2
5-3
2
DATA
1
3
4
1
1
30
1
Comments
Wake-up header detection
0: header detection on 9 ½ bits, as AT86RF211
1: header detection on 10 bits
Reset value: 0
Reserved, must be kept to reset value: (000)2
Data slicer reference tuning, when internal (0000)
Reset value: (1000)
Discriminator offset shift (high)'
0: no shift
1: output level shifted up
Reset value: 0
Discriminator offset shift (low)
0: no shift
1: output level shifted down
Reset value: 0
STOP
29
1
16
ISTU
2
0
(11111)
DATL
28-24
2
2
ADD
23
1
–
1
0
22
–
0
2
to (1111)
(001011111)
WPER
21-13
2
0894C–WIRE–11/08
AT86RF211S
2
–
0
0
(0000100)
WL1
12-6
2
47