AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet - Page 44
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AT86RF211SAHW
Manufacturer Part Number
AT86RF211SAHW
Description
Manufacturer
Atmel
Datasheet
1.AT86RF211SAHW.pdf
(64 pages)
Specifications of AT86RF211SAHW
Lead Free Status / Rohs Status
Compliant
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4.6.2.7
Table 4-29.
44
Name
nbit
init
0894C–WIRE–11/08
XTALRUN
DTR Register
DTR Overview in RF211S Mode
31-30
00
DTR contains the bits corresponding to the new features of the AT86RF211S.
Depending on the CTRL1[0] value, DTR has two different sizes:
The DTR register enables the data slicer input offset to be precisely adjusted.
Table 4-27.
The register’s reset value = (20)
Note:
Table 4-28.
The DTR register also allows you to take advantage of the additional digital features when CTRL1[0] has
been set to 1 (ADDFEAT). If CTRL1[0] = 1 and DTR is left to the default value, the AT86RF211S has the
same features as the RF211 (with one exception explained in Note 5 on
Name
nbit
init
Name
DSREF
DISCHIGH
DISCLOW
• CTRL1[0] = 0 - DTR[5:0] - (same as AT86RF211)
• CTRL1[0] = 1 - DTR[31:0] - (extended DTR)
When CTRL1[0] is left to the default value, AT86RF211S’ programming and features are the same as for
the AT86RF211.
SELCH
29
0
Overview in RF211 Mode
Detailed Description in RF211 Mode
Number of Bits
HOLDMODE
28
0
4
1
1
DSREF[3:0]
5-2
(1000)
16
2
XTAL205M
Comments
Data Slicer reference tuning, when reference is said to be internal
(0000)
Reset value: (1000)
Discriminator offset shift (high)
0: no shift
1: output level shifted up
Reset value: 0
Discriminator offset shift (low)
0: no shift
1: output level shifted down
Reset value: 0
27
0
2
to (1111)
DISCRANGE
2
2
26-25
(10)
2
DISCLPF
DISCHIGH
1
0
24
0
page
47).
e2v semiconductors SAS 2008
RSSICLK
23-22
AT86RF211S
10
DISCLOW
0
0
21
–
0
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