AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet - Page 46

• Manufacturer Part Number: AT86RF211SAHW
• Manufacturer: Atmel

Specifications of AT86RF211SAHW

• Lead Free Status / Rohs Status: Compliant

Table 4-30.
46
Name
RSSICLK
–
PORTEN
PORTPOL
PORTSEL
CLKOUTPUT
NEWDATACLK
SYNCDATAMSG
DATACLKEN
WUSYNC
0894C–WIRE–11/08
DTR Detailed Description in RF211S Mode (Continued)
Number of Bits
1
2
1
1
1
3
2
1
1
1
Comments
RSSI clock selection control
00: 80 kHz clock (12 µs)
01: 160 kHz clock (6 µs)
10: 320 kHz clock (3 µs)
11: 640 kHz clock (1.5 µs)
Reset value: (10)
Reserved. Must be kept to reset value 0
DIGOUT pin enable
0: no signal on DIGOUT
1: DIGOUT selected for output signal
Reset value: 0
DIGOUT pin polarity
0: low level for '0'
1: low level for '1', inverted output
Reset value: 0
DIGOUT signal selection
000: divided XTAL reference clock (see CLKOUTPUT below)
001: carrier Sense on RSSI over TRSSI
010: XTAL oscillator running flag
011: 455 kHz reference clock from the discriminator PLL
100: Receive mode flag during “wake-up mode” (WUEN =1)
101: Receive mode flag (other modes)
110: 1 kHz reference clock of the Wake-up timer
111: Lock Detect flag of the main PLL
Reset value: (000)
DIGOUT output clock division ratio
00: no division
10: divided by 4
Reset value: (10)
Clock recovery improved algorithm
0: standard clock recovery state machine, same as AT86RF211 for compatibility
1: improved clock recovery state machine, recommended
Reset value: 0
DATAMSG resynchronization
0: no resynchronization, as AT86RF211
1: DATAMSG resynchronized by DATACLK
Reset value: 0
DATACLK with RSSI inhibition
0: no inhibition
Reset value: 0
Improved wake-up header synchro detection (during “wake-up mode”)
0: standard header synchro, as AT86RF211
1: improved header synchro with wider duty cycle acceptance
Reset value: 0
2
2
2
...... ...... 01: divided by 2
...... ...... 11: divided by 8
...... 1: DATACLK inhibited if RSSI < TRSSI
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AT86RF211S